A Real Time Multiprocessor Application Development Environment Design And Implementation. - Nacer-Eddine Zergainoh; Thierry Maurin; Yves Sorel; Christophe Lavarenne (PDP, 1994)

Multilanguage design of heterogeneous systems. - Philippe Coste; Fabiano Hessel; P. LeMarrec; Zoltan Sugar; Mohamed Romdhani; Rodolph Suescun; Nacer-Eddine Zergainoh; Ahmed Amine Jerraya (CODES, 1999)

Communication Interface Synthesis for Multilanguage Specifications. - Fabiano Hessel; Philippe Coste; P. LeMarrec; Nacer-Eddine Zergainoh; Jean-Marc Daveau; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 1999)

Towards design and validation of mixed-technology SOCs. - Salvador Mir; Benoît Charlot; Gabriela Nicolescu; Philippe Coste; Fabien Parrain; Nacer-Eddine Zergainoh; Bernard Courtois; Ahmed Amine Jerraya; Márta Rencz (ACM Great Lakes Symposium on VLSI, 2000)

Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification. - Fabiano Hessel; Philippe Coste; Gabriela Nicolescu; P. LeMarrec; Nacer-Eddine Zergainoh; Ahmed Amine Jerraya (ICCD, 2000)

Generic Architecture Platform for Multiprocessor System-On-Chip Design. - Amer Baghdadi; Nacer-Eddine Zergainoh; Damien Lyonnard; Ahmed Amine Jerraya (DIPES, 2000)

Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip. - Nacer-Eddine Zergainoh; Amer Baghdadi; Ludovic Tambour; Damien Lyonnard; Lovic Gauthier; Ahmed Amine Jerraya (DIPES, 2000)

Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems. - Amer Baghdadi; Nacer-Eddine Zergainoh; Wander O. Cesário; T. Roudier; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2000)

Interlanguage Communication Synthesis for Heterogeneous Specifications. - Fabiano Hessel; Pascal Coste; Philippe Le Marrec; Nacer-Eddine Zergainoh; Gabriela Nicolescu; Jean-Marc Daveau; Ahmed Amine Jerraya (Des. Autom. Embed. Syst., 2000)

An efficient architecture model for systematic design of application-specific multiprocessor SoC. - Amer Baghdadi; Damien Lyonnard; Nacer-Eddine Zergainoh; Ahmed Amine Jerraya (DATE, 2001)

Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems. - Amer Baghdadi; Nacer-Eddine Zergainoh; Wander O. Cesário; Ahmed Amine Jerraya (IEEE Trans. Software Eng., 2002)

Exploration de l'espace des solutions architecturales dans le codesign. - Amer Baghdadi; Nacer-Eddine Zergainoh; Wander O. Cesário; Ahmed Amine Jerraya (Tech. Sci. Informatiques, 2002)

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. - Youngchul Cho; Ganghee Lee; Kiyoung Choi; Sungjoo Yoo; Nacer-Eddine Zergainoh (Embedded Software for SoC, 2003)

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. - Youngchul Cho; Ganghee Lee; Sungjoo Yoo; Kiyoung Choi; Nacer-Eddine Zergainoh (DATE, 2003)

An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells. - Ludovic Tambour; Nacer-Eddine Zergainoh; Pascal Urard; Henri Michel; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2003)

A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip. - Nacer-Eddine Zergainoh; Amer Baghdadi; Ahmed Amine Jerraya (Ann. des Télécommunications, 2004)

Scheduler implementation in MP SoC design. - Youngchul Cho; Sungjoo Yoo; Kiyoung Choi; Nacer-Eddine Zergainoh; Ahmed Amine Jerraya (ASP-DAC, 2005)

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems. - Nacer-Eddine Zergainoh; Katalin Popovici; Ahmed Amine Jerraya; Pascal Urard (ASP-DAC, 2005)

Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip. - Nacer-Eddine Zergainoh; Amer Baghdadi; Ahmed Amine Jerraya (Int. J. Embed. Syst., 2005)

Méthodes de correction de retard dans les modèles RTL des systèmes monopuces DSP obtenus par assemblage de composants IP : fondement théorique et implémentation. - Nacer-Eddine Zergainoh; Ludovic Tambour; Henri Michel; Ahmed Amine Jerraya (Tech. Sci. Informatiques, 2005)

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems. - Nacer-Eddine Zergainoh; Ludovic Tambour; Pascal Urard; Ahmed Amine Jerraya (EURASIP J. Adv. Signal Process., 2006)

Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation. - Nacer-Eddine Zergainoh; Ludovic Tambour; Ahmed Amine Jerraya (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design. - Youssef Atat; Nacer-Eddine Zergainoh (ISVLSI, 2007)

Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. - Youngchul Cho; Nacer-Eddine Zergainoh; Kiyoung Choi; Ahmed Amine Jerraya (IEEE International Workshop on Rapid System Prototyping, 2007)

Buffer Size Reduction through Control-Flow Decomposition. - Youngchul Cho; Nacer-Eddine Zergainoh; Ahmed Amine Jerraya; Kiyoung Choi (RTCSA, 2007)

Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. - Youngchul Cho; Nacer-Eddine Zergainoh; Sungjoo Yoo; Ahmed Amine Jerraya; Kiyoung Choi (Des. Autom. Embed. Syst., 2007)

Variability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chip. - Gilles Bizot; Nacer-Eddine Zergainoh; Michael Nicolaidis (IOLTS, 2009)

Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems. - Fabien Chaix; Dimiter Avresky; Nacer-Eddine Zergainoh; Michael Nicolaidis (NCA, 2010)

On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS. - Pascal Vivet; Edith Beigné; Hugo Lebreton; Nacer-Eddine Zergainoh (PATMOS, 2010)

A fault-tolerant deadlock-free adaptive routing for on chip interconnects. - Fabien Chaix; Dimiter Avresky; Nacer-Eddine Zergainoh; Michael Nicolaidis (DATE, 2011)

Eliminating speed penalty in ECC protected memories. - Michael Nicolaidis; Thierry Bonnoit; Nacer-Eddine Zergainoh (DATE, 2011)

Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor. - Hai Yu; Michael Nicolaidis; Lorena Anghel; Nacer-Eddine Zergainoh (ETS, 2011)

Towards a tool for implementing delay-free ECC in embedded memories. - Thierry Bonnoit; Michael Nicolaidis; Nacer-Eddine Zergainoh (ICCD, 2011)

Variability-aware task mapping strategies for many-cores processor chips. - Fabien Chaix; Gilles Bizot; Michael Nicolaidis; Nacer-Eddine Zergainoh (IOLTS, 2011)

Self-Recovering Parallel Applications in Multi-core Systems. - Gilles Bizot; Dimiter Avresky; Fabien Chaix; Nacer-Eddine Zergainoh; Michael Nicolaidis (NCA, 2011)

On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling. - Pascal Vivet; Edith Beigné; Hugo Lebreton; Nacer-Eddine Zergainoh (J. Low Power Electron., 2011)

Design for test and reliability in ultimate CMOS. - Michael Nicolaidis; Lorena Anghel; Nacer-Eddine Zergainoh; Yervant Zorian; Tanay Karnik; Keith A. Bowman; James W. Tschanz; Shih-Lien Lu; Carlos Tokunaga; Arijit Raychowdhury; Muhammad M. Khellah; Jaydeep Kulkarni; et al. (DATE, 2012)

Variability-aware and fault-tolerant self-adaptive applications for many-core chips. - Gilles Bizot; Fabien Chaix; Nacer-Eddine Zergainoh; Michael Nicolaidis (IOLTS, 2013)

Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip. - Michael G. Dimopoulos; Yi Gang; Mounir Benabdenbi; Lorena Anghel; Nacer-Eddine Zergainoh; Michael Nicolaidis (IOLTS, 2013)

Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study. - Thierry Bonnoit; Michael Nicolaidis; Nacer-Eddine Zergainoh (J. Electron. Test., 2013)

A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis. - Fabien Chaix; Nacer-Eddine Zergainoh; Michael Nicolaidis (ETS, 2014)

Preliminary results of SEU fault-injection on multicore processors in AMP mode. - Vanessa Vargas; Pablo Ramos; Wassim Mansour; Raoul Velazco; Nacer-Eddine Zergainoh; Jean-François Méhaut (IOLTS, 2014)

Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip. - Michael G. Dimopoulos; Yi Gang; Lorena Anghel; Mounir Benabdenbi; Nacer-Eddine Zergainoh; Michael Nicolaidis (Microprocess. Microsystems, 2014)

MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip. - Amir Charif; Nacer-Eddine Zergainoh; Michael Nicolaidis (IOLTS, 2015)

Evaluating SEU fault-injection on parallel applications implemented on multicore processors. - Vanessa Vargas; Pablo Ramos; Raoul Velazco; Jean-François Méhaut; Nacer-Eddine Zergainoh (LASCAS, 2015)

A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs. - Amir Charif; Nacer-Eddine Zergainoh; Michael Nicolaidis (DFT, 2016)

Addressing transient routing errors in fault-tolerant Networks-on-Chips. - Amir Charif; Nacer-Eddine Zergainoh; Michael Nicolaidis (ETS, 2016)

Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU. - Amir Charif; Alexandre Coelho; Nacer-Eddine Zergainoh; Michael Nicolaidis (ASP-DAC, 2017)

Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs. - Amir Charif; Nacer-Eddine Zergainoh; Alexandre Coelho; Michael Nicolaidis (ETS, 2017)

Low cost rollback to improve fault-tolerance in VLSI circuits. - Thierry Bonnoit; Nacer-Eddine Zergainoh; Michael Nicolaidis; Raoul Velazco (LASCAS, 2017)

SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core. - Thierry Bonnoit; Alexandre Coelho; Nacer-Eddine Zergainoh; Raoul Velazco (LATS, 2017)

MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips. - Amir Charif; Alexandre Coelho; Nacer-Eddine Zergainoh; Michael Nicolaidis (LATS, 2017)

Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs. - M. Solinas; Alexandre Coelho; Juan A. Fraire; Nacer-Eddine Zergainoh; Pablo A. Ferreyra; Raoul Velazco (LATS, 2017)

Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations. - Juan A. Fraire; Pablo G. Madoery; Scott C. Burleigh; Marius Feldmann; Jorge M. Finochietto; Amir Charif; Nacer-Eddine Zergainoh; Raoul Velazco (J. Comput. Networks Commun., 2017)

A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips. - Amir Charif; Alexandre Coelho; Nacer-Eddine Zergainoh; Michael Nicolaidis (VLSI Design, 2017)

Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution. - Thierry Bonnoit; Fraidy Bouesse; Nacer-Eddine Zergainoh; Michael Nicolaidis (DATE, 2018)

A soft-error resilient route computation unit for 3D Networks-on-Chips. - Alexandre Coelho; Amir Charif; Nacer-Eddine Zergainoh; Juan A. Fraire; Raoul Velazco (DATE, 2018)

A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip. - Alexandre Coelho; Amir Charif; Nacer-Eddine Zergainoh; Raoul Velazco (DFT, 2018)

First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip. - Amir Charif; Alexandre Coelho; Masoumeh Ebrahimi; Nader Bagherzadeh; Nacer-Eddine Zergainoh (IEEE Trans. Computers, 2018)

Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance. - Thierry Bonnoit; Nacer-Eddine Zergainoh; Michael Nicolaidis (IEEE Trans. Very Large Scale Integr. Syst., 2018)

NoCFI: A Hybrid Fault Injection Method for Networks-On-Chip. - Alexandre Coelho; Nacer-Eddine Zergainoh; Raoul Velazco (LATS, 2019)

A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips. - Amir Charif; Alexandre Coelho; Nacer-Eddine Zergainoh; Michael Nicolaidis (IEEE Trans. Emerg. Top. Comput., 2020)

X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective. - Nasr-Eddine Ouldei Tebina; Nacer-Eddine Zergainoh; Paolo Maistri (DFT, 2022)

Simulation Methodology for Assessing X-Ray Effects on Digital Circuits. - Nasr-Eddine Ouldei Tebina; Nacer-Eddine Zergainoh; Guillaume Hubert; Paolo Maistri (DFT, 2023)

Ray-Spect: Local Parametric Degradation for Secure Designs: An application to X-Ray Fault Injection. - Nasr-Eddine Ouldei Tebina; Laurent Maingault; Nacer-Eddine Zergainoh; Guillaume Hubert; Paolo Maistri (IOLTS, 2023)

Enhancing Side-Channel Attacks Through X-Ray-Induced Leakage Amplification. - Nasr-Eddine Ouldei Tebina; Luc Salvo; Laurent Maingault; Nacer-Eddine Zergainoh; Guillaume Hubert; Paolo Maistri (DATE, 2024)

Non-Invasive Attack on Ring Oscillator-Based PUFs Through Localized X-Ray Irradiation. - Nasr-Eddine Ouldei Tebina; Aghiles Douadi; Luc Salvo; Vincent Beroulle; Nacer-Eddine Zergainoh; Guillaume Hubert; Elena-Ioana Vatajelu; Giorgio Di Natale; Paolo Maistri (HOST, 2024)