Design Patterns for Reconfigurable Computing. - André DeHon; Joshua Adams; Michael DeLorimier; Nachiket Kapre; Yuki Matsuda 007; Helia Naeimi; Michael C. Vanier; Michael G. Wrighton (FCCM, 2004)

GraphStep: A System Architecture for Sparse-Graph Algorithms. - Michael DeLorimier; Nachiket Kapre; Nikil Mehta; Dominic Rizzo; Ian Eslick; Raphael Rubin; Tomás E. Uribe; Thomas F. Knight Jr.; André DeHon (FCCM, 2006)

Packet Switched vs. Time Multiplexed FPGA Overlay Networks. - Nachiket Kapre; Nikil Mehta; Michael DeLorimier; Raphael Rubin; Henry Barnor; Michael J. Wilson; Michael G. Wrighton; André DeHon (FCCM, 2006)

Optimistic Parallelization of Floating-Point Accumulation. - Nachiket Kapre; André DeHon (IEEE Symposium on Computer Arithmetic, 2007)

Accelerating SPICE Model-Evaluation using FPGAs. - Nachiket Kapre; André DeHon (FCCM, 2009)

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors. - Nachiket Kapre; André DeHon (FPL, 2009)

Pipelining Saturated Accumulation. - Karl Papadantonakis; Nachiket Kapre; Stephanie Chan; André DeHon (IEEE Trans. Computers, 2009)

An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph Applications. - Nachiket Kapre; André DeHon (ReCoSoC, 2010)

VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration. - Nachiket Kapre; André DeHon (FPT, 2011)

An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads. - Nachiket Kapre; André DeHon (Int. J. Reconfigurable Comput., 2011)

Spatial hardware implementation for sparse graph algorithms in GraphStep. - Michael DeLorimier; Nachiket Kapre; Nikil Mehta; André DeHon (ACM Trans. Auton. Adapt. Syst., 2011)

SPICE²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator. - Nachiket Kapre (2011)

A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem. - Abid Rafique; Nachiket Kapre; George A. Constantinides (ARC, 2012)

FX-SCORE: A Framework for Fixed-Point Compilation of SPICE Device Models Using Gappa++. - Hélène Martorell; Nachiket Kapre (FCCM, 2012)

Enhancing performance of Tall-Skinny QR factorization using FPGAs. - Abid Rafique; Nachiket Kapre; George A. Constantinides (FPL, 2012)

${ rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA. - Nachiket Kapre; André DeHon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Exploiting Input Parameter Uncertainty for Reducing Datapath Precision of SPICE Device Models. - Nachiket Kapre (FCCM, 2013)

Application Composition and Communication Optimization in Iterative Solvers Using FPGAs. - Abid Rafique; Nachiket Kapre; George A. Constantinides (FCCM, 2013)

System-level FPGA device driver with high-level synthesis support. - Kizheppatt Vipin; Shanker Shreejith; Dulitha Gunasekera; Suhaib A. Fahmy; Nachiket Kapre (FPT, 2013)

Breaking Sequential Dependencies in FPGA-Based Sparse LU Factorization. - Siddhartha 001; Nachiket Kapre (FCCM, 2014)

Timing Fault Detection in FPGA-Based Circuits. - Edward A. Stott; Joshua M. Levine; Peter Y. K. Cheung; Nachiket Kapre (FCCM, 2014)

MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations. - Deheng Ye; Nachiket Kapre (FCCM, 2014)

Comparing soft and hard vector processing in FPGA-based embedded systems. - Soh Jun Jie; Nachiket Kapre (FPL, 2014)

Heterogeneous dataflow architectures for FPGA-based sparse LU factorization. - Siddhartha 001; Nachiket Kapre (FPL, 2014)

Analysis and optimization of a deeply pipelined FPGA soft processor. - Hui Yan Cheah; Suhaib A. Fahmy; Nachiket Kapre (FPT, 2014)

Fanout decomposition dataflow optimizations for FPGA-based Sparse LU factorization. - Siddhartha 001; Nachiket Kapre (FPT, 2014)

Relax-Miracle: GPU parallelization of semi-analytic fourier-domain solvers for earthquake modeling. - Sagar Shrishailappa Masuti; Sylvain Barbot; Nachiket Kapre (HiPC, 2014)

Custom FPGA-based soft-processors for sparse graph acceleration. - Nachiket Kapre (ASAP, 2015)

Energy-Efficient Acceleration of OpenCV Saliency Computation Using Soft Vector Processors. - Gopalakrishna Hegde; Nachiket Kapre (FCCM, 2015)

Sparse Graph Processing with Soft-Processors. - Nachiket Kapre (FCCM, 2015)

Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing. - Nachiket Kapre; Bibin Chandrashekaran; Harnhua Ng; Kirvy Teo (FCCM, 2015)

Zedwulf: Power-Performance Tradeoffs of a 32-Node Zynq SoC Cluster. - Pradeep Moorthy; Nachiket Kapre (FCCM, 2015)

InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters. - Nachiket Kapre; Harnhua Ng; Kirvy Teo; Jaco Naude (FPGA, 2015)

FPGA Acceleration of Irregular Iterative Computations using Criticality-Aware Dataflow Optimizations (Abstract Only). - Siddhartha 001; Nachiket Kapre (FPGA, 2015)

On Data Forwarding in Deeply Pipelined Soft Processors. - Hui Yan Cheah; Suhaib A. Fahmy; Nachiket Kapre (FPGA, 2015)

Hoplite: Building austere overlay NoCs for FPGAs. - Nachiket Kapre; Jan Gray (FPL, 2015)

Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications. - Nachiket Kapre; Jayakrishnan Selva Kumar; Parjanya Gupta; Sagar Shrishailappa Masuti; Sylvain Barbot (FPL, 2015)

Enhancing Speedups for FPGA Accelerated SPICE through Frequency Scaling and Precision Reduction. - Lim Hui Hui; Nachiket Kapre (IPDPS Workshops, 2015)

GraphMMU: Memory Management Unit for Sparse Graph Accelerators. - Nachiket Kapre; Han Jianglei; Andrew Bean; Pradeep Moorthy; Siddhartha 001 (IPDPS Workshops, 2015)

G-DMA: improving memory access performance for hardware accelerated sparse graph computation. - Andrew Bean; Nachiket Kapre; Peter Y. K. Cheung (ReConFig, 2015)

A Case for Embedded FPGA-based SoCs in Energy-Efficient Acceleration of Graph Problems. - Nachiket Kapre; Pradeep Moorthy (Supercomput. Front. Innov., 2015)

Communication Optimization of Iterative Sparse Matrix-Vector Multiply on GPUs and FPGAs. - Abid Rafique; George A. Constantinides; Nachiket Kapre (IEEE Trans. Parallel Distributed Syst., 2015)

CaffePresso: an optimized library for deep learning on embedded accelerator-based platforms. - Gopalakrishna Hegde; Siddhartha 001; Nachiappan Ramasamy; Nachiket Kapre (CASES, 2016)

Preventive Detection of Mosquito Populations using Embedded Machine Learning on Low Power IoT Platforms. - Prashant Ravi; Uma Syam; Nachiket Kapre (ACM DEV, 2016)

Evaluating Embedded FPGA Accelerators for Deep Learning Applications. - Gopalakrishna Hegde; Siddhartha 001; Nachiappan Ramasamy; Vamsi Buddha; Nachiket Kapre (FCCM, 2016)

Marathon: Statically-Scheduled Conflict-Free Routing on FPGA Overlay NoCs. - Nachiket Kapre (FCCM, 2016)

Communication Optimization for the 16-Core Epiphany Floating-Point Processor Array. - Nachiket Kapre; Siddhartha 001 (FCCM, 2016)

Improving Classification Accuracy of a Machine Learning Approach for FPGA Timing Closure. - Que Yanghua; Nachiket Kapre; Harnhua Ng; Kirvy Teo (FCCM, 2016)

GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths. - Nachiket Kapre; Deheng Ye (FPGA, 2016)

Machine-Learning driven Auto-Tuning of High-Level Synthesis for FPGAs (Abstract Only). - Li Ting; Harri Wijaya; Nachiket Kapre (FPGA, 2016)

Case for Design-Specific Machine Learning in Timing Closure of FPGA Designs. - Que Yanghua; Chinnakkannu Adaikkala Raj; Harnhua Ng; Kirvy Teo; Nachiket Kapre (FPGA, 2016)

Hoplite-DSP: Harnessing the Xilinx DSP48 multiplexers to efficiently support NoCs on FPGAs. - Kumar H. B. Chethan; Nachiket Kapre (FPL, 2016)

Survey of domain-specific languages for FPGA computing. - Nachiket Kapre; Samuel Bayliss (FPL, 2016)

Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons. - Sidharth Maheshwari; Gourav Modi; Siddhartha 001; Nachiket Kapre (FPL, 2016)

Boosting convergence of timing closure using feature selection in a Learning-driven approach. - Que Yanghua; Harnhua Ng; Nachiket Kapre (FPL, 2016)

Deflection routing for multi-level FPGA overlay NoCs. - Kumar H. B. Chethan; Shubham Agarwal; Nachiket Kapre (FPT, 2016)

Learning to Extract API Mentions from Informal Natural Language Discussions. - Deheng Ye; Zhenchang Xing; Chee Yong Foo; Jing Li 034; Nachiket Kapre (ICSME, 2016)

Software-specific part-of-speech tagging: an experimental study on stack overflow. - Deheng Ye; Zhenchang Xing; Jing Li 034; Nachiket Kapre (SAC, 2016)

Software-Specific Named Entity Recognition in Software Engineering Social Content. - Deheng Ye; Zhenchang Xing; Chee Yong Foo; Zi Qun Ang; Jing Li 034; Nachiket Kapre (SANER, 2016)

Optimizing Soft Vector Processing in FPGA-Based Embedded Systems. - Nachiket Kapre (ACM Trans. Reconfigurable Technol. Syst., 2016)

eBSP: Managing NoC traffic for BSP workloads on the 16-core Adapteva Epiphany-III processor. - Siddhartha 001; Nachiket Kapre (DATE, 2017)

On Bit-Serial NoCs for FPGAs. - Nachiket Kapre (FCCM, 2017)

Implementing FPGA Overlay NoCs Using the Xilinx UltraScale Memory Cascades. - Nachiket Kapre (FCCM, 2017)

120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board. - Chethan Kumar H. B; Prashant Ravi; Gourav Modi; Nachiket Kapre (FPGA, 2017)

Deflection-routed butterfly fat trees on FPGAs. - Nachiket Kapre (FPL, 2017)

Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs. - Kizheppatt Vipin; Jan Gray; Nachiket Kapre (FPL, 2017)

HopliteRT: An efficient FPGA NoC for real-time applications. - Saud Wasly; Rodolfo Pellizzoni; Nachiket Kapre (FPT, 2017)

Applying Models of Computation to OpenCL Pipes for FPGA Computing. - Nachiket Kapre; Hiren D. Patel (IWOCL, 2017)

Out-of-Order Dataflow Scheduling for FPGA Overlays. - Siddhartha 001; Nachiket Kapre (CoRR, 2017)

The structure and dynamics of knowledge network in domain-specific Q&A sites: a case study of stack overflow. - Deheng Ye; Zhenchang Xing; Nachiket Kapre (Empir. Softw. Eng., 2017)

Hoplite: A Deflection-Routed Directional Torus NoC for FPGAs. - Nachiket Kapre; Jan Gray (ACM Trans. Reconfigurable Technol. Syst., 2017)

Hoplite-Q: Priority-Aware Routing in FPGA Overlay NoCs. - Siddhartha 001; Nachiket Kapre (FCCM, 2018)

LegUp-NoC: High-Level Synthesis of Loops with Indirect Addressing. - Asif Islam; Nachiket Kapre (FCCM, 2018)

FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only). - Nachiket Kapre; Tushar Krishna (FPGA, 2018)

DaCO: A High-Performance Token Dataflow Coprocessor Overlay for FPGAs. - Siddhartha 001; Nachiket Kapre (FPT, 2018)

Implementing NEF Neural Networks on Embedded FPGAs. - Benjamin Morcos; Terrence C. Stewart; Chris Eliasmith; Nachiket Kapre (FPT, 2018)

FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-Cost High-Performance Soft NoCs. - Nachiket Kapre; Tushar Krishna (ISCA, 2018)

CaffePresso: Accelerating Convolutional Networks on Embedded SoCs. - Gopalakrishna Hegde; Siddhartha 001; Nachiket Kapre (ACM Trans. Embed. Comput. Syst., 2018)

RapidRoute: Fast Assembly of Communication Structures for FPGA Overlays. - Leo Liu; Jay Weng; Nachiket Kapre (FCCM, 2019)

Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control. - Gurshaant Singh Malik; Nachiket Kapre (FCCM, 2019)

HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs. - Tushar Garg; Saud Wasly; Rodolfo Pellizzoni; Nachiket Kapre (FPGA, 2019)

Timing-Aware Routing in the RapidWright Framework. - Leo Liu; Nachiket Kapre (FPL, 2019)

Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems. - Ananda Samajdar; Tushar Garg; Tushar Krishna; Nachiket Kapre (FPL, 2019)

Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit. - Long Chung Chan; Gurshaant Malik; Nachiket Kapre (FPT, 2019)

Exploring The Impact Of Switch Arity On Butterfly Fat Tree Fpga Nocs. - Ian Elmor Lang; Ziqiang Huang; Nachiket Kapre (FCCM, 2020)

Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers. - Gurshaant Malik; Ian Elmor Lang; Rodolfo Pellizzoni; Nachiket Kapre (FPL, 2020)

RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms. - Niansong Zhang; Xiang Chen 007; Nachiket Kapre (FPL, 2020)

DarwiNN: efficient distributed neuroevolution under communication constraints. - Gurshaant Singh Malik; Lucian Petrica; Nachiket Kapre; Michaela Blott (GECCO Companion, 2020)

RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays using Evolutionary Algorithms. - Niansong Zhang; Xiang Chen; Nachiket Kapre (CoRR, 2020)

HopliteBuf: Network Calculus-Based Design of FPGA NoCs with Provably Stall-Free FIFOs. - Tushar Garg; Saud Wasly; Rodolfo Pellizzoni; Nachiket Kapre (ACM Trans. Reconfigurable Technol. Syst., 2020)

Mocarabe: High-Performance Time-Multiplexed Overlays for FPGAs. - Frederick Tombs; Alireza Mellat; Nachiket Kapre (FCCM, 2021)

Worst-case latency analysis for the versal NoC network packet switch. - Ian Elmor Lang; Nachiket Kapre; Rodolfo Pellizzoni (NOCS, 2021)

Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs. - Srinirdheeshwar Kuttuva Prakash; Hiren D. Patel; Nachiket Kapre (FCCM, 2022)

HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators. - Gurshaant Malik; Ian Elmor Lang; Rodolfo Pellizzoni; Nachiket Kapre (ACM Trans. Reconfigurable Technol. Syst., 2022)

RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm. - Niansong Zhang; Xiang Chen 007; Nachiket Kapre (ACM Trans. Reconfigurable Technol. Syst., 2022)

Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems. - Zhuanhao Wu; Marat Bekmyrza; Nachiket Kapre; Hiren D. Patel (DATE, 2023)

GraphNoC: Graph Neural Networks for Application-Specific FPGA NoC Performance Prediction. - Gurshaant Malik; Nachiket Kapre (ICFPT, 2024)