A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. - Keiichi Higeta; Masami Usami; Masayuki Ohayashi; Yasuhiro Fujimura; Masahiko Nishiyama; Satoru Isomura; Kunihiko Yamaguchi; Youji Idei; Hiroaki Nambu; Kenichi Ohhata; Nadateru Hanta (IEEE J. Solid State Circuits, 1996)