Network Facility for a Reconfigurable Computer Architecture. - Manjai Lee; Eric Fiene; Chuan-lin Wu; Geoffrey Brown; Nader Bagherzadeh (ICDCS, 1985)

Software Authorization Systems. - Paul A. Suhler; Nader Bagherzadeh; Miroslav Malek; Neil Iscoe (IEEE Softw., 1986)

Network simulation of synchronous garbage collection algorithm. - B. Kandu; Seng-lai Heng; Chuan-lin Wu; Nader Bagherzadeh (Simulation of Computer Networks, 1987)

Performance of symbolic applications on a parallel architecture. - Adolfo Guzmán; Edward J. Krall; Patrick F. McGehearty; Nader Bagherzadeh (Int. J. Parallel Program., 1987)

Near-optimal message routing and broadcasting in faulty hypercubes. - Douglas M. Blough; Nader Bagherzadeh (Int. J. Parallel Program., 1990)

A Percolation Based VLIW Architecture. - Arthur Abnous; Roni Potasman; Nader Bagherzadeh; Alexandru Nicolau (ICPP (1), 1991)

Parallel Hough Transform for Image Processing on a Pyramid Architecture. - Alireza Kavianpour; Nader Bagherzadeh (ICPP (1), 1991)

Hypermesh: A Combined Quad Tree and Mesh Network for Parallel Processing. - Wei Kang Tsai; Nader Bagherzadeh; Young C. Kim (ICPP (1), 1991)

Special Features of a VLIW Architecture. - Arthur Abnous; Nader Bagherzadeh (IPPS, 1991)

A Parallel Asynchronous Garbage Collection Algorithm for Distributed Systems. - Nader Bagherzadeh; Seng-lai Heng; Chuan-lin Wu (IEEE Trans. Knowl. Data Eng., 1991)

Optimal Ring Embedding in Hypercubes with Faulty Links. - Shahram Latifi; Si-Qing Zheng; Nader Bagherzadeh (FTCS, 1992)

On Design and Performance Analysis of a Superscalar Architecture. - Takaaki Kato; Koji Suginuma; Nader Bagherzadeh (ICPP (1), 1992)

Parallel Implementation of the Auction Algorithm on the Intel Hypercube. - Nader Bagherzadeh; Kent Hawk (IPPS, 1992)

Performance analysis and design methodology for a scalable superscalar architecture. - Takaaki Kato; Toshihisa Ono; Nader Bagherzadeh (MICRO, 1992)

Design and implementation of the 'Tiny RISC' microprocessor. - Arthur Abnous; Christopher Christensen; Jeffrey Gray; John Lenell; Andrew Naylor; Nader Bagherzadeh (Microprocess. Microsystems, 1992)

Finding circular shapes in an image on a pyramid architecture. - Alireza Kavianpour; Nader Bagherzadeh (Pattern Recognit. Lett., 1992)

The Star Connected Cycles: A Fixed-Degree Network for Parallel Processing. - Shahram Latifi; Marcelo M. de Azevedo; Nader Bagherzadeh (ICPP (1), 1993)

The Clustered-Star Graph: A New Topology for Large Interconnection Networks. - Shahram Latifi; Nader Bagherzadeh (IPPS, 1993)

A Routing and Broadcasting Scheme on Faulty Star Graphs. - Nader Bagherzadeh; Nayla Nassif; Shahram Latifi (IEEE Trans. Computers, 1993)

A Systematic Approch for Mapping Application Tasks in Hypercubes. - Alireza Kavianpour; Nader Bagherzadeh (IEEE Trans. Computers, 1993)

VIPER: a VLIW integer microprocessor. - Jeffrey Gray; Andrew Naylor; Arthur Abnous; Nader Bagherzadeh (IEEE J. Solid State Circuits, 1993)

Parallel Algorithms for Line Detection on A Pyramid Architecture. - Alireza Kavianpour; Nader Bagherzadeh (Int. J. Pattern Recognit. Artif. Intell., 1994)

Pyramid simulation of image processing applications. - S. Shoari; Alireza Kavianpour; Nader Bagherzadeh (Image Vis. Comput., 1994)

A New Approach for Circle Detection on Multiprocessors. - Alireza Kavianpour; S. Shoari; Nader Bagherzadeh (J. Parallel Distributed Comput., 1994)

A performance comparison of several superscalar processor models with a VLIW processor. - John Lenell; Nader Bagherzadeh (Microprocess. Microsystems, 1994)

Pipelining and Bypassing in a VLIW Processor. - Arthur Abnous; Nader Bagherzadeh (IEEE Trans. Parallel Distributed Syst., 1994)

Incomplete Star: An Incrementally Scalable Network Based on the Star Graph. - Shahram Latifi; Nader Bagherzadeh (IEEE Trans. Parallel Distributed Syst., 1994)

Fault-diameter of the star-connected cycles interconnection network. - Marcelo M. de Azevedo; Nader Bagherzadeh; Shahram Latifi (HICSS (2), 1995)

Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. - Steven Wallace; Nirav Dagli; Nader Bagherzadeh (ICCD, 1995)

Broadcasting Algorithms for the Star-Connected Cycles Interconnection Network. - Marcelo M. de Azevedo; Nader Bagherzadeh; Shahram Latifi (J. Parallel Distributed Comput., 1995)

Performance issues of a superscalar microprocessor. - Steven Wallace; Nader Bagherzadeh (Microprocess. Microsystems, 1995)

A Well-Behaved Enumeration of Star Graphs. - Nader Bagherzadeh; Martin Dowd; Shahram Latifi (IEEE Trans. Parallel Distributed Syst., 1995)

A fine-grain multithreading superscalar architecture. - M. Loikkanen; Nader Bagherzadeh (IEEE PACT, 1996)

A scalable register file architecture for dynamically scheduled processors. - Steven Wallace; Nader Bagherzadeh (IEEE PACT, 1996)

Variable-Dilation Embeddings of Hypercubes into Star Graphs: Performance Metrics, Mapping Functions, and Routing. - Marcelo Moraes de Azevdeo; Nader Bagherzadeh; Shahram Latifi (Euro-Par, Vol. I, 1996)

Instruction Fetching Mechanisms for Superscalar Microprocessors. - Steven Wallace; Nader Bagherzadeh (Euro-Par, Vol. II, 1996)

Performance Study of a Multithreaded Superscalar Microprocessor. - Manu Gulati; Nader Bagherzadeh (HPCA, 1996)

Hamiltonicity of the Clustered-Star Graph with Embedding Applications. - Shahram Latifi; Nader Bagherzadeh (PDPTA, 1996)

Average distance and routing algorithms in the star-connected cycles interconnection network. - Marcelo M. de Azevedo; Nader Bagherzadeh; Martin Dowd; Shahram Latifi (SPDP, 1996)

Some Topological Properties of Star Connected Cycles. - Marcelo M. de Azevedo; Nader Bagherzadeh; Martin Dowd; Shahram Latifi (Inf. Process. Lett., 1996)

A Grid Embedding into the Star Graph for Image Analysis Solutions. - Nayla Nassif; Nader Bagherzadeh (Inf. Process. Lett., 1996)

Embedding an Arbitrary Binary Tree into the Star Graph. - Nader Bagherzadeh; Martin Dowd; Nayla Nassif (IEEE Trans. Computers, 1996)

Multiple Branch and Block Prediction. - Steven Wallace; Nader Bagherzadeh (HPCA, 1997)

On Embedding Rings into a Star-Related Network. - Shahram Latifi; Nader Bagherzadeh (Inf. Sci., 1997)

MorphoSys: A Reconfigurable Architecture for Multimedia Applications. - Hartej Singh; Ming-Hau Lee; Guangming Lu; Fadi J. Kurdahi; Nader Bagherzadeh (SBCCI, 1998)

A scalable register file architecture for superscalar processors. - Steven Wallace; Nader Bagherzadeh (Microprocess. Microsystems, 1998)

A parallel algorithm for pulsed laser infrared tomography. - S. Shoari; Nader Bagherzadeh; D. Goodman; Thomas E. Milner; D. J. Smithies; J. Stuart Nelson (Pattern Recognit. Lett., 1998)

Faster column operations in star networks. - Nader Bagherzadeh; Martin Dowd; Shahram Latifi (Telecommun. Syst., 1998)

Low Expansion Packings and Embeddings of Hypercubes into Star Graphs: A Performance-Oriented Approach. - Marcelo M. de Azevedo; Nader Bagherzadeh; Shahram Latifi (IEEE Trans. Parallel Distributed Syst., 1998)

Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors. - Steven Wallace; Nader Bagherzadeh (IEEE Trans. Parallel Distributed Syst., 1998)

Kernel Scheduling in Reconfigurable Computing. - Rafael Maestre; Fadi J. Kurdahi; Nader Bagherzadeh; Hartej Singh; Román Hermida; Milagros Fernández (DATE, 1999)

The MorphoSys Dynamically Reconfigurable System-on-Chip. - Guangming Lu; Hartej Singh; Ming-Hau Lee; Nader Bagherzadeh; Fadi J. Kurdahi; Eliseu M. Chaves Filho; Vladimir Castro Alves (Evolvable Hardware, 1999)

The MorphoSys Parallel Reconfigurable System. - Guangming Lu; Hartej Singh; Ming-Hau Lee; Nader Bagherzadeh; Fadi J. Kurdahi; Eliseu M. Chaves Filho (Euro-Par, 1999)

MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application. - Guangming Lu; Ming-Hau Lee; Hartej Singh; Nader Bagherzadeh; Fadi J. Kurdahi; Eliseu M. Chaves Filho (IPPS/SPDP Workshops, 1999)

A Framework for Scheduling and Context Allocation in Reconfigurable Computing. - Rafael Maestre; Milagros Fernández; Román Hermida; Nader Bagherzadeh (ISSS, 1999)

MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. - Hartej Singh; Guangming Lu; Eliseu M. Chaves Filho; Rafael Maestre; Ming-Hau Lee; Fadi J. Kurdahi; Nader Bagherzadeh (DAC, 2000)

Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. - Rafael Maestre; Milagros Fernández; Román Hermida; Fadi J. Kurdahi; Nader Bagherzadeh; Hartej Singh (FCCM, 2000)

Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization. - Rafael Maestre; Fadi J. Kurdahi; Milagros Fernández; Nader Bagherzadeh; Hartej Singh (ISSS, 2000)

Guest Editors' Introduction: Configurable Computing. - Fadi J. Kurdahi; Nader Bagherzadeh; Peter Athanas; Jose L. Muñoz (IEEE Des. Test Comput., 2000)

MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. - Hartej Singh; Ming-Hau Lee; Guangming Lu; Fadi J. Kurdahi; Nader Bagherzadeh; Eliseu M. Chaves Filho (IEEE Trans. Computers, 2000)

Design and Implementation of the MorphoSys Reconfigurable Computing Processor. - Ming-Hau Lee; Hartej Singh; Guangming Lu; Nader Bagherzadeh; Fadi J. Kurdahi; Eliseu M. Chaves Filho; Vladimir Castro Alves (J. VLSI Signal Process., 2000)

A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. - Girish Venkataramani; Walid A. Najjar; Fadi J. Kurdahi; Nader Bagherzadeh; A. P. Wim Böhm (CASES, 2001)

A constraint-based application model and scheduling techniques for power-aware systems. - Jinfeng Liu 006; Pai H. Chou; Nader Bagherzadeh; Fadi J. Kurdahi (CODES, 2001)

Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems. - Jinfeng Liu 006; Pai H. Chou; Nader Bagherzadeh; Fadi J. Kurdahi (DAC, 2001)

A data scheduler for multi-context reconfigurable architectures. - Marcos Sánchez-Élez; Milagros Fernández; Román Hermida; Rafael Maestre; Fadi J. Kurdahi; Nader Bagherzadeh (ISSS, 2001)

Design and implementation of Automatic Parallel Detection Layer. - Mohamed Ahamed Mead; Hesham Eldeeb; Salwa M. Nassar; Nader Bagherzadeh (SMC, 2001)

Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing. - Rafael Maestre; Fadi J. Kurdahi; Milagros Fernández; Román Hermida; Nader Bagherzadeh; Hartej Singh (J. Syst. Archit., 2001)

A formal approach to context scheduling for multicontext reconfigurable architectures. - Rafael Maestre; F. Kurdahl; Milagros Fernández; Román Hermida; Nader Bagherzadeh; Hartej Singh (IEEE Trans. Very Large Scale Integr. Syst., 2001)

A framework for reconfigurable computing: task scheduling and context management. - Rafael Maestre; Fadi J. Kurdahi; Milagros Fernández; Román Hermida; Nader Bagherzadeh; Hartej Singh (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Communication speed selection for embedded systems with networked voltage-scalable processors. - Jinfeng Liu 006; Pai H. Chou; Nader Bagherzadeh (CODES, 2002)

A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. - Marcos Sánchez-Élez; Milagros Fernández; Rafael Maestre; Román Hermida; Nader Bagherzadeh; Fadi J. Kurdahi (DATE, 2002)

Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches. - Manuel Lois Anido; Alexander Paar; Nader Bagherzadeh (DSD, 2002)

A Novel Predication Scheme for a SIMD System-on-Chip. - Alexander Paar; Manuel L. Anido; Nader Bagherzadeh (Euro-Par, 2002)

MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note). - Hooman Parizi; Afshin Niktash; Nader Bagherzadeh; Fadi J. Kurdahi (Euro-Par, 2002)

Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors. - Nader Bagherzadeh; Pai H. Chou; Jinfeng Liu 006 (ISSS, 2002)

Recovering 3D Metric Structure and Motion from Multiple Uncalibrated Cameras. - Miguel Sainz; Nader Bagherzadeh; Antonio Susín (ITCC, 2002)

Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources. - Jinfeng Liu 006; Pai H. Chou; Nader Bagherzadeh (PACS, 2002)

Interactive Ray Tracing Using a SIMD Reconfigurable Architecture. - Manuel L. Anido; Nader Bagherzadeh; Nozar Tabrizi; Haitao Du; Marcos Sánchez-Élez (SBAC-PAD, 2002)

A Novel Method for Improving the Operation Autonomy of SIMD Processing Elements. - Manuel Lois Anido; Alexander Paar; Nader Bagherzadeh (SBCCI, 2002)

Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. - Dexin Li; Pai H. Chou; Nader Bagherzadeh (ASP-DAC/VLSI Design, 2002)

IMPACCT: Methodology and Tools for Power-Aware Embedded Systems. - Pai H. Chou; Jinfeng Liu 006; Dexin Li; Nader Bagherzadeh (Des. Autom. Embed. Syst., 2002)

Interactive Ray Tracing on Reconfigurable SIMD Morphosys. - Haitao Du; Marcos Sánchez-Élez; Nozar Tabrizi; Nader Bagherzadeh; Manuel L. Anido; Milagros Fernández (Embedded Software for SoC, 2003)

Interactive ray tracing on reconfigurable SIMD MorphoSys. - Haitao Du; Marcos Sánchez-Élez; Nozar Tabrizi; Nader Bagherzadeh; Manuel Lois Anido; Milagros Fernández (ASP-DAC, 2003)

Topology selection for energy minimization in embedded networks. - Dexin Li; Pai H. Chou; Nader Bagherzadeh (ASP-DAC, 2003)

Adaptive computing: what can it do, where can it go? - Robert Reuss; Jose L. Muñoz; Toshiaki Miyazaki; Nader Bagherzadeh; Prith Banerjee; Brad L. Hutchings; Brian Schott (ASP-DAC, 2003)

A fast parallel reed-solomon decoder on a reconfigurable architecture. - Arezou Koohi; Nader Bagherzadeh; Chengzi Pan (CODES+ISSS, 2003)

Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver. - Chengzhi Pan; Nader Bagherzadeh; Amir Hosein Kamalizad; Arezou Koohi (DATE, 2003)

Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. - Marcos Sánchez-Élez; Milagros Fernández; Manuel L. Anido; Haitao Du; Nader Bagherzadeh; Román Hermida (DATE, 2003)

A Component Oriented Simulator for HW/SW Co-Designs. - Alexander Paar; Haitao Du; Nader Bagherzadeh (ESTIMedia, 2003)

Persepolis: Recovering history with a handheld camera. - Miguel Sainz; Antonio Susín; A. Cervantes; Nader Bagherzadeh (Eurographics (Posters), 2003)

Camera calibration of long image sequences with the presence of occlusions. - Miguel Sainz; Antonio Susín; Nader Bagherzadeh (ICIP (1), 2003)

Fast Parallel FFT on a Reconfigurable Computation Platform. - Amir Hosein Kamalizad; Chengzhi Pan; Nader Bagherzadeh (SBAC-PAD, 2003)

Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture. - Marcos Sánchez-Élez; Haitao Du; Nozar Tabrizi; Yun Long; Nader Bagherzadeh; Milagros Fernández (Comput. Graph., 2003)

Automatic compilation to a coarse-grained reconfigurable system-opn-chip. - Girish Venkataramani; Walid A. Najjar; Fadi J. Kurdahi; Nader Bagherzadeh; A. P. Wim Böhm; Jeffrey Hammes (ACM Trans. Embed. Comput. Syst., 2003)

Fast and efficient voltage scheduling by evolutionary slack distribution. - Bita Gorjiara; Pai H. Chou; Nader Bagherzadeh; Mehrdad Reshadi; David W. Jensen (ASP-DAC, 2004)

MaRS: a macro-pipelined reconfigurable system. - Nozar Tabrizi; Nader Bagherzadeh; Amir Hosein Kamalizad; Haitao Du (Conf. Computing Frontiers, 2004)

Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. - Fredy Rivera; Marcos Sánchez-Élez; Milagros Fernández; Román Hermida; Nader Bagherzadeh (CODES+ISSS, 2004)

An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes. - Bita Gorjiara; Nader Bagherzadeh; Pai H. Chou (ISLPED, 2004)

Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform. - Amir Hosein Kamalizad; Richard Plettner; Chengzhi Pan; Nader Bagherzadeh (SoCC, 2004)

A Programmable DSP Architecture for Wireless Communication Systems. - Amir Hosein Kamalizad; Nozar Tabrizi; Nader Bagherzadeh; Akira Hatanaka (ASAP, 2005)

An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures. - Fredy Rivera; Milagros Fernández; Nader Bagherzadeh (DSD, 2005)

Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures. - Fredy Rivera; Marcos Sánchez-Élez; Milagros Fernández; Román Hermida; Nader Bagherzadeh (IPDPS, 2005)

Increasing the throughput of an adaptive router in network-on-chip (NoC). - Seung Eun Lee; Nader Bagherzadeh (CODES+ISSS, 2006)

Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys). - Javier Davila; Alfonso de Torres; Jose Manuel Sanchez; Marcos Sánchez-Élez; Nader Bagherzadeh; Fredy Rivera (DATE Designers' Forum, 2006)

Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. - Fredy Rivera; Marcos Sánchez-Élez; Milagros Fernández; Román Hermida; Nader Bagherzadeh (FPL, 2006)

A Reconfigurable Architecture for Wireless Communication Systems. - Hooman Parizi; Afshin Niktash; Amir Hosein Kamalizad; Nader Bagherzadeh (ITNG, 2006)

A Multi-Standard Viterbi Decoder for Mobile Applications Using a Reconfigurable Architecture. - Afshin Niktash; Hooman Parizi; Nader Bagherzadeh (VTC Fall, 2006)

A Reconfigurable Processor for Forward Error Correction. - Afshin Niktash; Hooman Parizi; Nader Bagherzadeh (ARCS, 2007)

Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost. - Bita Gorjiara; Nader Bagherzadeh; Pai H. Chou (ASP-DAC, 2007)

Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures. - Fredy Rivera; Marcos Sánchez-Élez; Nader Bagherzadeh (ERSA, 2007)

A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template. - Akira Hatanaka; Nader Bagherzadeh (IPDPS, 2007)

Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless Systems. - Afshin Niktash; Hooman Parizi; Nader Bagherzadeh (ISCAS, 2007)

On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture. - Jun Ho Bahn; Seung Eun Lee; Nader Bagherzadeh (ITNG, 2007)

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). - Seung Eun Lee; Jun Ho Bahn; Nader Bagherzadeh (SBAC-PAD, 2007)

Design of a router for network-on-chip. - Jun Ho Bahn; Seung Eun Lee; Nader Bagherzadeh (Int. J. High Perform. Syst. Archit., 2007)

Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling. - Bita Gorjiara; Nader Bagherzadeh; Pai H. Chou (ACM Trans. Design Autom. Electr. Syst., 2007)

A Generic Network Interface Architecture for a Networked Processor Array (NePA). - Seung Eun Lee; Jun Ho Bahn; Yoon Seok Yang; Nader Bagherzadeh (ARCS, 2008)

Specific Absorption Rate Calculation using Parallel 3D Finite Difference Time Domain Technique. - Hala Elsadek; Hesham Eldeeb; Haytham Abdallah; Maha Eldesouky; Nader Bagherzadeh (Communications in Computing, 2008)

Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture. - Jun Ho Bahn; Nader Bagherzadeh (CSICC, 2008)

LocSens - An Indoor Location Tracking System using Wireless Sensors. - Faruk Bagci; Florian Kluge; Nader Bagherzadeh; Theo Ungerer (ICCCN, 2008)

ESTR - Energy Saving Token Ring Protocol for Wireless Sensor Networks. - Faruk Bagci; Theo Ungerer; Nader Bagherzadeh (ICWN, 2008)

Self-optimized Routing in a Network on-a-Chip. - Wolfgang Trumler; Sebastian Schlingmann; Theo Ungerer; Jun Ho Bahn; Nader Bagherzadeh (BICC, 2008)

Parallel FFT Algorithms on Network-on-Chips. - Jun Ho Bahn; Jungsook Yang; Nader Bagherzadeh (ITNG, 2008)

RECFEC: A Reconfigurable FEC Processor for Viterbi, Turbo, Reed-Solomon and LDPC Coding. - Afshin Niktash; Hooman Parizi; Amir Hosein Kamalizad; Nader Bagherzadeh (WCNC, 2008)

Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router. - Jun Ho Bahn; Nader Bagherzadeh (IET Comput. Digit. Tech., 2008)

Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures. - Fredy Rivera; Marcos Sánchez-Élez; Román Hermida; Nader Bagherzadeh (IET Comput. Digit. Tech., 2008)

An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator. - Nozar Tabrizi; Nader Bagherzadeh (Integr., 2008)

On Design and Application Mapping of a Network-on-Chip(NoC) Architecture. - Jun Ho Bahn; Seung Eun Lee; Yoon Seok Yang; Jungsook Yang; Nader Bagherzadeh (Parallel Process. Lett., 2008)

Mobile Agents for Wireless Sensor Networks. - Faruk Bagci; Julian Wolf 002; Theo Ungerer; Nader Bagherzadeh (ICWN, 2009)

Low power adaptive pipeline based on instruction isolation. - Seung Eun Lee; Chris Wilkerson; Ming Zhang; Rajendra S. Yavatkar; Shih-Lien Lu; Nader Bagherzadeh (ISQED, 2009)

Scheduling Techniques for Multi-Core Architectures. - Akira Hatanaka; Nader Bagherzadeh (ITNG, 2009)

Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip. - Yoon Seok Yang; Jun Ho Bahn; Seung Eun Lee; Nader Bagherzadeh (ITNG, 2009)

Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform. - Wen-Hsiang Hu; Jun Ho Bahn; Nader Bagherzadeh (SBAC-PAD, 2009)

Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system. - Radha Guha; Nader Bagherzadeh; Pai H. Chou (Comput. Electr. Eng., 2009)

A high level power model for Network-on-Chip (NoC) router. - Seung Eun Lee; Nader Bagherzadeh (Comput. Electr. Eng., 2009)

Optimisations for LocSens - an indoor location tracking system using wireless sensors. - Faruk Bagci; Florian Kluge; Theo Ungerer; Nader Bagherzadeh (Int. J. Sens. Networks, 2009)

A variable frequency link for a power-aware network-on-chip (NoC). - Seung Eun Lee; Nader Bagherzadeh (Integr., 2009)

Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip. - Nader Bagherzadeh; Masaru Matsuura (J. Circuits Syst. Comput., 2009)

Parallel FFT Algorithms on Network-on-Chips. - Jun Ho Bahn; Jungsook Yang; Wen-Hsiang Hu; Nader Bagherzadeh (J. Circuits Syst. Comput., 2009)

A framework for low energy data management in reconfigurable multi-context architectures. - Marcos Sánchez-Élez; Nader Bagherzadeh; Román Hermida (J. Syst. Archit., 2009)

Message Driven Programming with S-Net: Methodology and Performance. - Frank Penczek; Stephan Herhut; Sven-Bodo Scholz; Alexander V. Shafarenko; Jungsook Yang; Chun-Yi Chen; Nader Bagherzadeh; Clemens Grelck (ICPP Workshops, 2010)

A scalable delay insensitive asynchronous NoC with adaptive routing. - Abdulaziz Alhussien; Chifeng Wang; Nader Bagherzadeh (ICT, 2010)

Area and Power-efficient Innovative Network-on-Chip Architecurte. - Chifeng Wang; Wen-Hsiang Hu; Seung Eun Lee; Nader Bagherzadeh (PDP, 2010)

Parallel processing for block ciphers on a fault tolerant networked processor array. - Yoon Seok Yang; Jun Ho Bahn; Seung Eun Lee; Jungsook Yang; Nader Bagherzadeh (Int. J. High Perform. Syst. Archit., 2010)

A Wireless Network-on-Chip Design for Multicore Platforms. - Chifeng Wang; Wen-Hsiang Hu; Nader Bagherzadeh (PDP, 2011)

Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform. - Jungsook Yang; Chuny Chun; Nader Bagherzadeh; Seung Eun Lee (PDP, 2011)

A scheduling approach for distributed resource architectures with scarce communication resources. - Akira Hatanaka; Nader Bagherzadeh (Int. J. High Perform. Syst. Archit., 2011)

Special issue on: On-chip parallel and network-based systems. - Nader Bagherzadeh; Hamid Sarbazi-Azad (J. Syst. Archit., 2011)

Area and power-efficient innovative congestion-aware Network-on-Chip architecture. - Chifeng Wang; Wen-Hsiang Hu; Seung Eun Lee; Nader Bagherzadeh (J. Syst. Archit., 2011)

LATEX: New Selection Policy for Adaptive Routing in Application-Specific NoC. - Sanaz Azampanah; Ahmad Khademzadeh; Nader Bagherzadeh; Majid Janidarmian; Reza Shojaee (PDP, 2012)

A formally verified deadlock-free routing function in a fault-tolerant NoC architecture. - Abdulaziz Alhussien; Nader Bagherzadeh; Freek Verbeek; Bernard van Gastel; Julien Schmaltz (SBCCI, 2012)

Design and evaluation of a high throughput robust router for network-on-chip. - Abdulaziz Alhussien; Chifeng Wang; Nader Bagherzadeh (IET Comput. Digit. Tech., 2012)

Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform. - W.-H. Hu; C.-Y. Chen; Jun Ho Bahn; Nader Bagherzadeh (IET Comput. Digit. Tech., 2012)

High-throughput differentiated service provision router architecture for wireless network-on-chip. - Chifeng Wang; Nader Bagherzadeh (Int. J. High Perform. Syst. Archit., 2012)

Mapping and Scheduling in Heterogeneous NoC through Population-Based Incremental Learning. - Freddy Bolanos; Jose Edison Aedo; Fredy Rivera; Nader Bagherzadeh (J. Univers. Comput. Sci., 2012)

Editorial notes: Special issue on on-chip parallel and network-based systems. - Hamid Sarbazi-Azad; Nader Bagherzadeh (Microprocess. Microsystems, 2012)

A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms. - Chifeng Wang; Wen-Hsiang Hu; Nader Bagherzadeh (Microprocess. Microsystems, 2012)

A software pipelining algorithm of streaming applications with low buffer requirements. - Akira Hatanaka; Nader Bagherzadeh (Sci. Iran., 2012)

On heterogeneous network-on-chip design based on constraint programming. - Ayhan Demiriz; Nader Bagherzadeh (NoCArc@MICRO, 2013)

CPNoC: On Using Constraint Programming in Design of Network-on-Chip Architecture. - Ayhan Demiriz; Nader Bagherzadeh; Abdulaziz Alhussien (PDP, 2013)

Quality of Service Optimization for Network-on-Chip Using Bandwidth-Constraint Mapping Algorithm. - Azadeh Eskandari; Ahmad Khademzadeh; Nader Bagherzadeh; Majid Janidarmian (PDP, 2013)

Contention-aware selection strategy for application-specific network-on-chip. - Sanaz Azampanah; Ahmad Khademzadeh; Nader Bagherzadeh; Majid Janidarmian; Reza Shojaee (IET Comput. Digit. Tech., 2013)

Multicore computing systems: Architecture, programming tools, and applications. - Hamid Sarbazi-Azad; Nader Bagherzadeh (J. Comput. Syst. Sci., 2013)

Scalable load balancing congestion-aware Network-on-Chip router architecture. - Chifeng Wang; Wen-Hsiang Hu; Nader Bagherzadeh (J. Comput. Syst. Sci., 2013)

From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations. - Freddy Bolanos; Fredy Rivera; Jose Edison Aedo; Nader Bagherzadeh (J. Syst. Archit., 2013)

Efficient multicast schemes for 3-D Networks-on-Chip. - Xiaohang Wang 001; Mei Yang 001; Yingtao Jiang; Maurizio Palesi; Peng Liu 016; Terrence S. T. Mak; Nader Bagherzadeh (J. Syst. Archit., 2013)

TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip. - Ashkan Eghbal; Pooria M. Yaghini; Siavash S. Yazdi; Nader Bagherzadeh (DFT, 2014)

A GALS Router for Asynchronous Network-on-Chip. - Pooria M. Yaghini; Ashkan Eghbal; Nader Bagherzadeh (MES, 2014)

Voltage island based heterogeneous NoC design through constraint programming. - Ayhan Demiriz; Nader Bagherzadeh; Özcan Özturk 001 (Comput. Electr. Eng., 2014)

Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata. - Shaahin Angizi; Esam Alkaldy; Nader Bagherzadeh; Keivan Navi (J. Low Power Electron., 2014)

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip. - Chifeng Wang; Nader Bagherzadeh (Microprocess. Microsystems, 2014)

Ultra-low-power adder stage design for exascale floating point units. - Alberto A. Del Barrio; Nader Bagherzadeh; Román Hermida (ACM Trans. Embed. Comput. Syst., 2014)

High-Efficient Circuits for Ternary Addition. - Reza Faghih Mirzaee; Keivan Navi; Nader Bagherzadeh (VLSI Design, 2014)

Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC. - Pooria M. Yaghini; Ashkan Eghbal; Siavash S. Yazdi; Nader Bagherzadeh (NOCS, 2015)

An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip. - Ronak Salamat; Masoumeh Ebrahimi; Nader Bagherzadeh (PDP, 2015)

Capacitive Coupling Mitigation for TSV-based 3D ICs. - Ashkan Eghbal; Pooria M. Yaghini; Nader Bagherzadeh (VTS, 2015)

Special issue on on-chip parallel and network-based systems. - Masoud Daneshtalab; Nader Bagherzadeh; Hamid Sarbazi-Azad (Computing, 2015)

Using constraint programming for the design of network-on-chip architectures. - Ayhan Demiriz; Nader Bagherzadeh; Abdulaziz Alhussein (Computing, 2015)

Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic. - Masoomeh Jasemi; Reza Faghih Mirzaee; Keivan Navi; Nader Bagherzadeh (IET Circuits Devices Syst., 2015)

On-chip parallel and network-based systems. - Masoud Daneshtalab; Nader Bagherzadeh; Hamid Sarbazi-Azad (Integr., 2015)

On the design of hybrid routing mechanism for mesh-based network-on-chip. - Pooria M. Yaghini; Ashkan Eghbal; Nader Bagherzadeh (Integr., 2015)

Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops. - Shaahin Angizi; Samira Sayedsalehi; Arman Roohi; Nader Bagherzadeh; Keivan Navi (J. Circuits Syst. Comput., 2015)

Analytical Reliability Analysis of 3D NoC under TSV Failure. - Misagh Khayambashi; Pooria M. Yaghini; Ashkan Eghbal; Nader Bagherzadeh (ACM J. Emerg. Technol. Comput. Syst., 2015)

An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder. - Shaahin Angizi; Fahimeh Danehdaran; Soheil Sarmadi; Shadi Sheikhfaal; Nader Bagherzadeh; Keivan Navi (J. Low Power Electron., 2015)

Designing quantum-dot cellular automata counters with energy consumption analysis. - Shaahin Angizi; Mohammad Hossein Moaiyeri; Shohreh Farrokhi; Keivan Navi; Nader Bagherzadeh (Microprocess. Microsystems, 2015)

Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach. - Fazel Sharifi; Mohammad Hossein Moaiyeri; Keivan Navi; Nader Bagherzadeh (Microelectron. J., 2015)

Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip. - Ashkan Eghbal; Pooria M. Yaghini; Nader Bagherzadeh; Misagh Khayambashi (IEEE Trans. Computers, 2015)

Design and analysis of a mesh-based wireless network-on-chip. - Wen-Hsiang Hu; Chifeng Wang; Nader Bagherzadeh (J. Supercomput., 2015)

Advances in multicore systems architectures. - Hamid Sarbazi-Azad; Nader Bagherzadeh; G. Jaberipour (J. Supercomput., 2015)

Coupling Mitigation in 3-D Multiple-Stacked Devices. - Pooria M. Yaghini; Ashkan Eghbal; Misagh Khayambashi; Nader Bagherzadeh (IEEE Trans. Very Large Scale Integr. Syst., 2015)

ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects. - Freek Verbeek; Pooria M. Yaghini; Ashkan Eghbal; Nader Bagherzadeh (DATE, 2016)

CoBRA: Low cost compensation of TSV failures in 3D-NoC. - Ronak Salamat; Masoumeh Ebrahimi; Nader Bagherzadeh; Freek Verbeek (DFT, 2016)

Introduction to the Special Section on On-chip parallel and network-based systems. - Hamid Sarbazi-Azad; Nader Bagherzadeh; Masoumeh Ebrahimi; Masoud Daneshtalab (Comput. Electr. Eng., 2016)

Design of quaternary 4-2 and 5-2 compressors for nanotechnology. - Fazel Sharifi; Atiyeh Panahi; Hojjat Sharifi; Keivan Navi; Nader Bagherzadeh; Himanshu Thapliyal (Comput. Electr. Eng., 2016)

An Efficient Analog-to-Digital Converter Based on Carbon Nanotube FETs. - Mohammad Hossein Moaiyeri; Nooshin Khastoo; Molood Nasiri; Keivan Navi; Nader Bagherzadeh (J. Low Power Electron., 2016)

Ternary cyclic redundancy check by a new hardware-friendly ternary operator. - Mahya Sam Daliri; Reza Faghih Mirzaee; Keivan Navi; Nader Bagherzadeh (Microelectron. J., 2016)

A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs. - Ronak Salamat; Misagh Khayambashi; Masoumeh Ebrahimi; Nader Bagherzadeh (IEEE Trans. Computers, 2016)

Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks. - Hesam Shabani; Arman Roohi; Akram Reza; Midia Reshadi; Nader Bagherzadeh; Ronald F. DeMara (IEEE Trans. Computers, 2016)

Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs. - Pooria M. Yaghini; Ashkan Eghbal; Siavash S. Yazdi; Nader Bagherzadeh; Michael M. Green (IEEE Trans. Computers, 2016)

Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation. - Michael Opoku Agyeman; Ali Ahmadinia; Nader Bagherzadeh (IEEE Trans. Parallel Distributed Syst., 2016)

Online monitoring and adaptive routing for aging mitigation in NoCs. - Zana Ghaderi; Ayed Alqahtani 001; Nader Bagherzadeh (DATE, 2017)

A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates. - Mahya Sam Daliri; Keivan Navi; Reza Faghih Mirzaee; Nader Bagherzadeh (IET Circuits Devices Syst., 2017)

Method for designing ternary adder cells based on CNFETs. - Sepehr Tabrizchi; Atiyeh Panahi; Fazel Sharifi; Keivan Navi; Nader Bagherzadeh (IET Circuits Devices Syst., 2017)

High-performance ternary operators for scrambling. - Mahya Sam Daliri; Reza Faghih Mirzaee; Keivan Navi; Nader Bagherzadeh (Integr., 2017)

Towards Approximate Computing with Quantum-Dot Cellular Automata. - Zahra Rouhani; Shaahin Angizi; MohammadReza Taheri; Keivan Navi; Nader Bagherzadeh (J. Low Power Electron., 2017)

Quantum-dot cellular automata circuits with reduced external fixed inputs. - Milad Bagherian Khosroshahy; Mohammad Hossein Moaiyeri; Shaahin Angizi; Nader Bagherzadeh; Keivan Navi (Microprocess. Microsystems, 2017)

A Single Parity-Check Digit for One Trit Error Detection in Ternary Communication Systems: Gate-Level and Transistor-Level Designs. - Reza Faghih Mirzaee; Mahya Sam Daliri; Keivan Navi; Nader Bagherzadeh (J. Multiple Valued Log. Soft Comput., 2017)

SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs. - Zana Ghaderi; Mohammad Ebrahimi; Zainalabedin Navabi; Eli Bozorgzadeh; Nader Bagherzadeh (IEEE Trans. Computers, 2017)

Deadlock Verification of Cache Coherence Protocols and Communication Fabrics. - Freek Verbeek; Pooria M. Yaghini; Ashkan Eghbal; Nader Bagherzadeh (IEEE Trans. Computers, 2017)

A General Fault-Tolerant Minimal Routing for Mesh Architectures. - Hongzhi Zhao; Nader Bagherzadeh; Jie Wu (IEEE Trans. Computers, 2017)

Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks. - Min Soo Kim 003; Alberto A. Del Barrio; Román Hermida; Nader Bagherzadeh (ASP-DAC, 2018)

HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressors. - Ahmad Albaqsami; Maryam S. Hosseini; Nader Bagherzadeh (DATE, 2018)

CompStor: An In-storage Computation Platform for Scalable Distributed Processing. - Mahdi Torabzadehkashi; Siavash Rezaei; Vladimir Castro Alves; Nader Bagherzadeh (IPDPS Workshops, 2018)

Divisible Load Scheduling of Image Processing Applications on the Heterogeneous Star Network Using a new Genetic Algorithm. - Sahar Nikbakht Aali; Hadi Shahriar Shahhoseini; Nader Bagherzadeh (PDP, 2018)

Simulation-Based Evaluation Strategy for Task Mapping Approaches in WNoC Platforms. - Luis German Garcia Morales; Jose Edinson Aedo Cobo; Nader Bagherzadeh (PDP, 2018)

Application partitioning and mapping for bypass channel based NoC. - Fatemeh Khodaparast 001; Midia Reshadi; Nader Bagherzadeh (Comput. Electr. Eng., 2018)

Reducing bypass-based network-on-chip latency using priority mechanism. - Amir Fadakar Noghondar; Midia Reshadi; Nader Bagherzadeh (IET Comput. Digit. Tech., 2018)

Hospital enterprise Architecture Framework (Study of Iranian University Hospital Organization). - Atefehsadat Haghighathoseini; Hossein Bobarshad; Fatehmeh Saghafi; Mohammad Sadegh Rezaei; Nader Bagherzadeh (Int. J. Medical Informatics, 2018)

An energy and area efficient 4: 2 compressor based on FinFETs. - Armineh Arasteh; Mohammad Hossein Moaiyeri; MohammadReza Taheri; Keivan Navi; Nader Bagherzadeh (Integr., 2018)

System-Level Analysis of 3D ICs with Thermal TSVs. - Ayed Alqahtani 001; Zongqing Ren; Jaeho Lee; Nader Bagherzadeh (ACM J. Emerg. Technol. Comput. Syst., 2018)

Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata. - Fahimeh Danehdaran; Milad Bagherian Khosroshahy; Keivan Navi; Nader Bagherzadeh (J. Low Power Electron., 2018)

Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip. - Michael Opoku Agyeman; Ali Ahmadinia; Nader Bagherzadeh (J. Syst. Archit., 2018)

First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip. - Amir Charif; Alexandre Coelho; Masoumeh Ebrahimi; Nader Bagherzadeh; Nacer-Eddine Zergainoh (IEEE Trans. Computers, 2018)

STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs. - Zana Ghaderi; Nader Bagherzadeh; Ahmad Albaqsami (IEEE Trans. Computers, 2018)

LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification. - Ronak Salamat; Misagh Khayambashi; Masoumeh Ebrahimi; Nader Bagherzadeh (IEEE Trans. Computers, 2018)

A Compositional Approach for Verifying Protocols Running on On-Chip Networks. - Freek Verbeek; Pooria M. Yaghini; Ashkan Eghbal; Nader Bagherzadeh (IEEE Trans. Computers, 2018)

Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption. - Shaahin Angizi; Zhezhi He; Nader Bagherzadeh; Deliang Fan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Ultra-Efficient Fuzzy Min/Max Circuits Based on Carbon Nanotube FETs. - Ali Bozorgmehr; Mohammad Hossein Moaiyeri; Keivan Navi; Nader Bagherzadeh (IEEE Trans. Fuzzy Syst., 2018)

AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs. - Zana Ghaderi; Ayed Alqahtani 001; Nader Bagherzadeh (IEEE Trans. Parallel Distributed Syst., 2018)

A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks. - Hyun Jin Kim 001; Min Soo Kim 003; Alberto A. Del Barrio; Nader Bagherzadeh (ARITH, 2019)

Power and Performance Optimal NoC Design for CPU-GPU Architecture Using Formal Models. - Lulwah Alhubail; Nader Bagherzadeh (DATE, 2019)

Efficient Deep Neural Networks for Edge Computing. - Mohammed Alnemari; Nader Bagherzadeh (EDGE, 2019)

Design of Power-Efficient FPGA Convolutional Cores with Approximate Log Multiplier. - Leonardo Tavares Oliveira; Min Soo Kim 003; Alberto A. Del Barrio García; Nader Bagherzadeh; Ricardo Menotti (ESANN, 2019)

Accelerating HPC Applications Using Computational Storage Devices. - Mahdi Torabzadehkashi; Ali Heydarigorji; Siavash Rezaei; Hossein Bobarshad; Vladimir Castro Alves; Nader Bagherzadeh (HPCC/SmartCity/DSS, 2019)

A Radiation Hard Sense Circuit for Spin Transfer Torque Random Access Memory. - Saba Mohammadi; Masoomeh Jasemi; Seyed Mohammadjavad Seyed Talebi; Nader Bagherzadeh; Michael M. Green (ISCAS, 2019)

Flow mapping and data distribution on mesh-based deep learning accelerator. - Seyedeh Yasaman Hosseini Mirmahaleh; Midia Reshadi; Hesam Shabani; Xiaochen Guo; Nader Bagherzadeh (NOCS, 2019)

Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics. - Mahdi Torabzadehkashi; Siavash Rezaei; Ali Heydarigorji; Hossein Bobarshad; Vladimir Castro Alves; Nader Bagherzadeh (PDP, 2019)

Partition Pruning: Parallelization-Aware Pruning for Deep Neural Networks. - Sina Shahhosseini; Ahmad Albaqsami; Masoomeh Jasemi; Shaahin Hessabi; Nader Bagherzadeh (CoRR, 2019)

Novel CNFET ternary circuit techniques for high-performance and energy-efficient design. - Sepehr Tabrizchi; MohammadReza Taheri; Keivan Navi; Nader Bagherzadeh (IET Circuits Devices Syst., 2019)

DICA: destination intensity and congestion-aware output selection strategy for network-on-chip systems. - Amin Mehranzadeh; Ahmad Khademzadeh; Nader Bagherzadeh; Midia Reshadi (IET Comput. Digit. Tech., 2019)

Computational storage: an efficient and scalable platform for big data and HPC applications. - Mahdi Torabzadehkashi; Siavash Rezaei; Ali Heydarigorji; Hossein Bobarshad; Vladimir Castro Alves; Nader Bagherzadeh (J. Big Data, 2019)

A new approach to the Population-Based Incremental Learning algorithm using virtual regions for task mapping on NoCs. - Luis German Garcia Morales; Jose Edinson Aedo Cobo; Nader Bagherzadeh (J. Syst. Archit., 2019)

CLBM: Controlled load-balancing mechanism for congestion management in silicon interposer NoC architecture. - Mona Soleymani; Midia Reshadi; Nader Bagherzadeh; Ahmad Khademzadeh (J. Syst. Archit., 2019)

Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology. - Maryam Toulabinejad; MohammadReza Taheri; Keivan Navi; Nader Bagherzadeh (Microelectron. J., 2019)

Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks. - Min Soo Kim 003; Alberto A. Del Barrio; Leonardo Tavares Oliveira; Román Hermida; Nader Bagherzadeh (IEEE Trans. Computers, 2019)

Supervised Machine-Learning Algorithms in Real-time Prediction of Hypotensive Events. - Mina Chookhachizadeh Moghadam; Ehsan Masoumi Khalil Abad; Nader Bagherzadeh; Davinder Ramsingh; Zeev N. Kain (EMBC, 2020)

NoC Design Methodologies for Heterogeneous Architecture. - Lulwah Alhubail; Masoomeh Jasemi; Nader Bagherzadeh (PDP, 2020)

Partition Pruning: Parallelization-Aware Pruning for Dense Neural Networks. - Sina Shahhosseini; Ahmad Albaqsami; Masoomeh Jasemi; Nader Bagherzadeh (PDP, 2020)

A Fine-Grained Source-Throttling Method for Mesh Architectures. - Hongzhi Zhao; Nader Bagherzadeh; Qiang Wang; Yongchang Wang (IEEE Access, 2020)

A machine-learning approach to predicting hypotensive events in ICU settings. - Mina Chookhachizadeh Moghadam; Ehsan Masoumi Khalil Abad; Nader Bagherzadeh; Davinder Ramsingh; Guann-Pyng Li; Zeev N. Kain (Comput. Biol. Medicine, 2020)

A novel digital fuzzy system for image edge detection based on wrap-gate carbon nanotube transistors. - Ali Bozorgmehr; Mohammad Khaleqi Qaleh Jooq; Mohammad Hossein Moaiyeri; Keivan Navi; Nader Bagherzadeh (Comput. Electr. Eng., 2020)

Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators. - Masoomeh Jasemi; Shaahin Hessabi; Nader Bagherzadeh (Comput. Electr. Eng., 2020)

Divisible load scheduling of image processing applications on the heterogeneous star and tree networks using a new genetic algorithm. - Sahar Nikbakht Aali; Nader Bagherzadeh (Concurr. Comput. Pract. Exp., 2020)

Flow mapping on mesh-based deep learning accelerator. - Seyedeh Yasaman Hosseini Mirmahaleh; Midia Reshadi; Nader Bagherzadeh (J. Parallel Distributed Comput., 2020)

IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes. - Alireza Tajary; Hamid R. Zarandi; Nader Bagherzadeh (Microprocess. Microsystems, 2020)

Adaptive HTF-MPR: An Adaptive Heterogeneous TensorFlow Mapper Utilizing Bayesian Optimization and Genetic Algorithms. - Ahmad Albaqsami; Maryam S. Hosseini; Masoomeh Jasemi; Nader Bagherzadeh (ACM Trans. Intell. Syst. Technol., 2020)

Application Characterization for Near Memory Processing. - Maryam S. Hosseini; Masoumeh Ebrahimi; Pooria M. Yaghini; Nader Bagherzadeh (PDP, 2021)

Predicting hypotension in the ICU using noninvasive physiological signals. - Mina Chookhachizadeh Moghadam; Ehsan Masoumi Khalil Abad; Samir Kendale; Nader Bagherzadeh (Comput. Biol. Medicine, 2021)

Data scheduling and placement in deep learning accelerator. - Seyedeh Yasaman Hosseini Mirmahaleh; Midia Reshadi; Nader Bagherzadeh; Ahmad Khademzadeh (Clust. Comput., 2021)

PLAM: a Posit Logarithm-Approximate Multiplier for Power Efficient Posit-based DNNs. - Raul Murillo 001; Alberto A. Del Barrio; Guillermo Botella; Min Soo Kim 003; Hyunjin Kim 001; Nader Bagherzadeh (CoRR, 2021)

Enhancing Reliability of Emerging Memory Technology for Machine Learning Accelerators. - Masoomeh Jasemi; Shaahin Hessabi; Nader Bagherzadeh (IEEE Trans. Emerg. Top. Comput., 2021)

A High Performance, Multi-Bit Output Logic-in-Memory Adder. - Javad Talafy; Farzaneh Zokaee; Hamid R. Zarandi; Nader Bagherzadeh (IEEE Trans. Emerg. Top. Comput., 2021)

A Two-Stage Efficient 3-D CNN Framework for EEG Based Emotion Recognition. - Ye Qiao; Mohammed Alnemari; Nader Bagherzadeh (ICIT, 2022)

A storage-efficient ensemble classification using filter sharing on binarized convolutional neural networks. - Hyunjin Kim 001; Mohammed Alnemari; Nader Bagherzadeh (PeerJ Comput. Sci., 2022)

Near Volatile and Non-Volatile Memory Processing in 3D Systems. - Maryam S. Hosseini; Masoumeh Ebrahimi; Pooria M. Yaghini; Nader Bagherzadeh (IEEE Trans. Emerg. Top. Comput., 2022)

The Effects of Approximate Multiplication on Convolutional Neural Networks. - Min Soo Kim 003; Alberto A. Del Barrio; Hyun Jin Kim 001; Nader Bagherzadeh (IEEE Trans. Emerg. Top. Comput., 2022)

PLAM: A Posit Logarithm-Approximate Multiplier. - Raul Murillo 001; Alberto A. Del Barrio; Guillermo Botella; Min Soo Kim 003; Hyun Jin Kim 001; Nader Bagherzadeh (IEEE Trans. Emerg. Top. Comput., 2022)

Guest Editorial: Thematic Section on Applications of Emerging Computing Technologies in Smart Manufacturing and Industry 4.0. - Daniele Jahier Pagliari; Frank Schirrmeister; Nader Bagherzadeh; Enrico Macii (IEEE Trans. Emerg. Top. Comput., 2022)

Reversible quantum communication & systems. - Diganta Sengupta; Ahmed A. Abd El-Latif 001; Debashis De; Keivan Navi; Nader Bagherzadeh (IET Quantum Commun., 2022)

Stock Trend Prediction: A Semantic Segmentation Approach. - Shima Nabiee; Nader Bagherzadeh (CoRR, 2023)

Support for Stock Trend Prediction Using Transformers and Sentiment Analysis. - Harsimrat Kaeley; Ye Qiao; Nader Bagherzadeh (CoRR, 2023)

BNN An Ideal Architecture for Acceleration With Resistive in Memory Computation. - Andrew Ding; Ye Qiao; Nader Bagherzadeh (IEEE Trans. Emerg. Top. Comput., 2023)

Efficient realization of quantum balanced ternary reversible multiplier building blocks: A great step towards sustainable computing. - Ehsan Faghih; MohammadReza Taheri; Keivan Navi; Nader Bagherzadeh (Sustain. Comput. Informatics Syst., 2023)

ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks. - Ali Sedaghatgoo; Amir M. Hajisadeghi; Mahmoud Momtazpour; Nader Bagherzadeh (CoRR, 2024)

Guest Editorial: Special Section on "Approximate Data Processing: Computing, Storage and Applications". - Ke Chen 018; Shanshan Liu 001; Weiqiang Liu 001; Fabrizio Lombardi; Nader Bagherzadeh (IEEE Trans. Emerg. Top. Comput., 2024)