Welcome to the 55th IEEE international midwest symposium on circuits and systems (MWSCAS 2012). - Nader Rafla 001; Mohamad Sawan; José M. de la Rosa 001 (MWSCAS, 2012)

An automated embedded computer vision system for object measurement. - Nicholas Pauly; Nader I. Rafla (MWSCAS, 2013)

Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only). - Danyal Mohammadi; Said Ahmed-Zaid; Nader Rafla 001 (FPGA, 2015)

Zynq-based SoC implementation of an induction machine control algorithm. - Danyal Mohammadi; Luka Daoud; Nader Rafla 001; Said Ahmed-Zaid (MWSCAS, 2016)

High level synthesis using vivado HLS for optimizations of SHA-3. - H. S. Jacinto; Luka Daoud; Nader Rafla 001 (MWSCAS, 2017)

SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only). - Luka Daoud; Muhammad Kamran Latif; Nader Rafla 001 (FPGA, 2018)

HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only). - Fady Hussein; Luka Daoud; Nader Rafla 001 (FPGA, 2018)

Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration. - Luka Daoud; Fady Hussein; Nader Rafla 001 (MWSCAS, 2018)

Routing Aware and Runtime Detection for Infected Network-on-Chip Routers. - Luka Daoud; Nader Rafla 001 (MWSCAS, 2018)

Optimization of a Quantum-Secure Sponge-Based Hash Message Authentication Protocol. - Muhammad Kamran Latif; H. S. Jacinto; Luka Daoud; Nader Rafla 001 (MWSCAS, 2018)

Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS). - Luka Daoud; Fady Hussein; Nader Rafla 001 (CATA, 2019)

Analysis of Black Hole Router Attack in Network-on-Chip. - Luka Daoud; Nader Rafla 001 (MWSCAS, 2019)

Detection and prevention protocol for black hole attack in network-on-chip. - Luka Daoud; Nader Rafla 001 (NOCS, 2019)

Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip. - Luka Daoud; Nader Rafla 001 (SoCC, 2019)

HLS Implementation of Linear Discriminant Analysis Classifier. - Michael R. Wasef; Nader Rafla 001 (ISCAS, 2020)

Evaluating and Improving Child-Directed Automatic Speech Recognition. - Eric G. Booth; Jake Carns; Casey Kennington; Nader Rafla 001 (LREC, 2020)

A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching. - Luka Daoud; Muhammad Kamran Latif; H. S. Jacinto; Nader Rafla 001 (Microprocess. Microsystems, 2020)

A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA. - Fady Hussein; Luka Daoud; Nader Rafla 001 (Microprocess. Microsystems, 2020)

Hardware implementation of Multi-Rate input SoftMax activation function. - Michael R. Wasef; Nader Rafla 001 (MWSCAS, 2021)

Energy-Efficient Black Hole Router Detection in Network-on-Chip. - Luka Daoud; Nader Rafla 001 (SOCC, 2022)

Efficient mitigation technique for Black Hole router attack in Network-on-Chip. - Luka Daoud; Nader Rafla 001 (Microprocess. Microsystems, 2022)

SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA. - Michael R. Wasef; Nader Rafla 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Hardware Implementation of Image Processing Morphological and Convolution Operations as SoC on FPGAs. - Alfred M. Moussa; Richard Groves; Nader Rafla 001 (DMIP, 2024)

Enhanced Hardware Trojan Detection in Chips By Reducing Linearity Between Features. - Alfred Moussa; Nader Rafla 001 (MWSCAS, 2024)