Input waveform slope effects in CMOS delays. - Daniel Auvergne; Nadine Azémard; Denis Deschacht; Michel Robert (IEEE J. Solid State Circuits, 1990)

Formal sizing rules of CMOS circuits. - Daniel Auvergne; Nadine Azémard; V. Bonzom; Denis Deschacht; Michel Robert (EURO-DAC, 1991)

P.SIZE: a sizing aid for optimized designs. - Nadine Azémard; V. Bonzom; Daniel Auvergne (EURO-DAC, 1992)

Post-layout timing simulation of CMOS circuits. - Denis Deschacht; Michel Robert; Nadine Azémard-Crestani; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Explicit evaluation of short circuit power dissipation for CMOS logic structures. - S. Turgis; Nadine Azémard; Daniel Auvergne (ISLPD, 1995)

Design and selection of buffers for minimum power-delay product. - S. Turgis; Nadine Azémard; Daniel Auvergne (ED&TC, 1996)

Delay-power performance analysis. - S. Cremoux; M. Aline; Nadine Azémard; Daniel Auvergne (ICECS, 1999)

Feasible Delay Bound Definition. - Nadine Azémard; M. Aline; Philippe Maurine; Daniel Auvergne (VLSI-SOC, 2001)

Gate Sizing for Low Power Design. - Philippe Maurine; Nadine Azémard; Daniel Auvergne (VLSI-SOC, 2001)

Delay bound determination for timing closure satisfaction. - Nadine Azémard; M. Aline; Daniel Auvergne (ISCAS (5), 2001)

POPS: A tool for delay/power performance optimization. - Nadine Azémard; Daniel Auvergne (J. Syst. Archit., 2001)

Gate speed improvement at minimal power dissipation. - Philippe Maurine; Xavier Michel; Nadine Azémard; Daniel Auvergne (APCCAS (2), 2002)

Structure Independent Representation of Output Transition Time for CMOS Library. - Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2002)

Transition time modeling in deep submicron CMOS. - Philippe Maurine; Mustapha Rezzoug; Nadine Azémard; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Continuous representation of the performance of a CMOS library. - B. Lasbouygues; Joel Schindler; Sylvain Engels; Philippe Maurine; Nadine Azémard; Daniel Auvergne (ESSCIRC, 2003)

Metric Definition for Circuit Speed Optimization. - Xavier Michel; Alexandre Verle; Nadine Azémard; Philippe Maurine; Daniel Auvergne (PATMOS, 2003)

CMOS Gate Sizing under Delay Constraint. - Alexandre Verle; Xavier Michel; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2003)

Delay bound based CMOS gate sizing technique. - Alexandre Verle; Xavier Michel; Philippe Maurine; Nadine Azémard; Daniel Auvergne (ISCAS (5), 2004)

Design Optimization with Automated Cell Generation. - A. Landrault; Nadine Azémard; Philippe Maurine; Michel Robert; Daniel Auvergne (PATMOS, 2004)

Temperature Dependence in Low Power CMOS UDSM Process. - B. Lasbouygues; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Physical Extension of the Logical Effort Model. - B. Lasbouygues; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Performance Metric Based Optimization Protocol. - Xavier Michel; Alexandre Verle; Philippe Maurine; Nadine Azémard; Daniel Auvergne (PATMOS, 2004)

Low Power Oriented CMOS Circuit Optimization Protocol. - Alexandre Verle; Xavier Michel; Nadine Azémard; Philippe Maurine; Daniel Auvergne (DATE, 2005)

Circuit optimization based on speed indicators. - Alexandre Verle; A. Landrault; Philippe Maurine; Nadine Azémard (ICECS, 2005)

Temperature Dependency in UDSM Process. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (PATMOS, 2005)

Speed Indicators for Circuit Optimization. - Alexandre Verle; A. Landrault; Philippe Maurine; Nadine Azémard (PATMOS, 2005)

Request-skip adders : CMOS standard cell data dependent adders. - Robin Perrot; Nadine Azémard; Philippe Maurine (ICECS, 2006)

Circuit sizing method under delay constraint. - Alexandre Verle; A. Landrault; Philippe Maurine; Nadine Azémard (ISCAS, 2006)

Timing analysis in presence of supply voltage and temperature variations. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (ISPD, 2006)

Statistical Characterization of Library Timing Performance. - Vincent Migairou; Robin Wilson; Sylvain Engels; Nadine Azémard; Philippe Maurine (PATMOS, 2006)

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. - Sylvain Engels; Robin Wilson; Nadine Azémard; Philippe Maurine (Integr., 2006)

Logical effort model extension to propagation delay representation. - B. Lasbouygues; Sylvain Engels; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Temperature and voltage aware timing analysis: application to voltage drops. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (DATE, 2007)

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. - Vincent Migairou; Robin Wilson; Sylvain Engels; Zeqin Wu; Nadine Azémard; Philippe Maurine (PATMOS, 2007)

Temperature- and Voltage-Aware Timing Analysis. - B. Lasbouygues; Robin Wilson; Nadine Azémard; Philippe Maurine (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

SSTA considering switching process induced correlations. - Zeqin Wu; Philippe Maurine; Nadine Azémard; Gilles R. Ducharme (APCCAS, 2008)

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. - Bettina Rebaud; Marc Belleville; Christian Bernard; Zeqin Wu; Michel Robert; Philippe Maurine; Nadine Azémard (ISVLSI, 2008)

Editorial. - Nadine Azémard; Philippe Maurine; Johan Vounckx (Integr., 2008)

Product On-Chip Process Compensation for Low Power and Yield Enhancement. - Nabila Moubdi; Philippe Maurine; Robin Wilson; Nadine Azémard; Vincent Dumettier; Abhishek Bansal 003; Sebastien Barasinski; Alain Tournier; Guy Durieu; David Meyer; Pierre Busson; Sarah Verhaeren; et al. (PATMOS, 2009)

Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. - Bettina Rebaud; Marc Belleville; Edith Beigné; Christian Bernard; Michel Robert; Philippe Maurine; Nadine Azémard (PATMOS, 2009)

Interpreting SSTA Results with Correlation. - Zeqin Wu; Philippe Maurine; Nadine Azémard; Gilles R. Ducharme (PATMOS, 2009)

Timing margin evaluation with a simple statistical timing analysis flow. - Vincent Migairou; Robin Wilson; Sylvain Engels; Zeqin Wu; Nadine Azémard; Philippe Maurine (J. Embed. Comput., 2009)

Selected Peer-Reviewed Articles from the VARI 2010 Workshop. - Nadine Azémard (J. Low Power Electron., 2010)

On-Chip Process Variability Monitoring Flow. - Nabila Moubdi; Philippe Maurine; Robin Wilson; Sylvain Engels; Nadine Azémard; Vincent Dumettier; Pierre Busson (J. Low Power Electron., 2010)

Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. - Bettina Rebaud; Marc Belleville; Edith Beigné; Christian Bernard; Michel Robert; Philippe Maurine; Nadine Azémard (Microelectron. J., 2011)

Statistical timing characterization. - Zeqin Wu; Philippe Maurine; Nadine Azémard; Gilles R. Ducharme (ISSoC, 2012)

Selected Articles from the VARI 2011 Workshop. - Nadine Azémard; Marc Belleville (J. Low Power Electron., 2012)

Selected Articles from the VARI 2012 Workshop. - Nadine Azémard; Gilles Jacquemod (J. Low Power Electron., 2012)

Delay-correlation-aware SSTA based on conditional moments. - Zeqin Wu; Philippe Maurine; Nadine Azémard; Gilles R. Ducharme (Microelectron. J., 2012)

Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9-11, 2013. - Nadine Azémard; Jörg Henkel (J. Low Power Electron., 2014)

Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29-October 1, 2014. - Nadine Azémard; Eugeni García-Moreno (J. Low Power Electron., 2015)

Physical description and analysis of doped carbon nanotube interconnects. - Jie Liang; Liuyang Zhang; Nadine Azémard-Crestani; Pascal Nouet; Aida Todri-Sanial (PATMOS, 2016)

Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices. - Rida Kheirallah; Gilles R. Ducharme; Nadine Azémard (J. Low Power Electron., 2016)

Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015. - Ricardo Reis 001; Nadine Azémard (J. Low Power Electron., 2016)

Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic. - Nicolas Jeanniot; Gaël Pillonnet; Pascal Nouet; Nadine Azémard; Aida Todri-Sanial (ICRC, 2017)

Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management. - Rida Kheirallah; Jean-Marc Gallière; Nadine Azémard; Gilles R. Ducharme (PATMOS, 2018)

Energy Autonomous Wearable Sensors for Smart Healthcare: A Review. - Abhishek Singh Dahiya; Jerome Thireau; Jamila Boudaden; Swatchith Lal; Umair Gulzar; Yan Zhang; Thierry Gil; Nadine Azémard; Peter Ramm; Tim Kiessling; Cian O'Murchu; Fredrik Sebelius; et al. (CoRR, 2019)

Iterative Method for Performance Prediction Improvement of Integrated Circuits. - Gwenael Chaillou; Philippe Maurine; Jean-Marc Gallière; Nadine Azémard (DCIS, 2021)

Oscillatory Neural Networks for Edge AI Computing. - Corentin Delacour; Stefania Carapezzi; Madeleine Abernot; Gabriele Boschetto; Nadine Azémard; Jérémie Salles; Thierry Gil; Aida Todri-Sanial (ISVLSI, 2021)

A mixed-signal oscillatory neural network for scalable analog computations in phase domain. - Corentin Delacour; Stefania Carapezzi; Gabriele Boschetto; Madeleine Abernot; Thierry Gil; Nadine Azémard; Aida Todri-Sanial (Neuromorph. Comput. Eng., 2023)

Lagrange Oscillatory Neural Networks for Constraint Satisfaction and Optimization. - Corentin Delacour; Bram Haverkort; Filip Sabo; Nadine Azémard; Aida Todri-Sanial (CoRR, 2025)