Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. - Sudhakar M. Reddy; Irith Pomeranz; Nadir Z. Basturkmen; Xijiang Lin (VTS, 1999)

A Low Power Pseudo-Random BIST Technique. - Nadir Z. Basturkmen; Sudhakar M. Reddy; Irith Pomeranz (IOLTW, 2002)

Pseudo Random Patterns Using Markov Sources for Scan BIST. - Nadir Z. Basturkmen; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2002)

Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. - Nadir Z. Basturkmen; Sudhakar M. Reddy; Janusz Rajski (ASP-DAC/VLSI Design, 2002)

Diagnosis of Scan Clock Failures. - King Leong Lee; Nadir Z. Basturkmen; Srikanth Venkataraman (VTS, 2008)