Functional verification of the IBM System z10 processor chipset. - Christopher A. Krygowski; Dean G. Bair; Rebecca M. Gott; Mark H. Decker; A. V. Giri; Christian Habermann; Matthias Heizmann; Stefan Letz; William J. Lewis; Steven M. Licker; H. Mallar; Edward C. McCain; et al. (IBM J. Res. Dev., 2009)

Insight into Application Performance Using Application-Dependent Characteristics. - Waleed Alkohlani; Jeanine E. Cook; Nafiul Siddique (PMBS@SC, 2014)

LMStr: Local memory store the case for hardware controlled scratchpad memory for general purpose processors. - Nafiul Alam Siddique; Abdel-Hameed A. Badawy; Jeanine E. Cook; David Resnick (IPCCC, 2016)

Can Architecture Design Help Eliminate Some Common Vulnerabilities? - Strahinja Trecakov; Casey Tran; Hameed Badawy; Nafiul Siddique; Jaime Acosta; Satyajayant Misra (MASS, 2017)

SprBlk cache: enabling fault resilience at low voltages. - Nafiul Alam Siddique; Abdel-Hameed A. Badawy (MEMSYS, 2017)

LMStr: exploring shared hardware controlled scratchpad memory for multicores. - Nafiul Alam Siddique; Abdel-Hameed A. Badawy; Jeanine E. Cook; David Resnick (MEMSYS, 2017)

Spare block cache (SprBlk): Fault resilience and reliability at low voltages. - Nafiul Alam Siddique; Abdel-Hameed A. Badawy (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI, 2017)

Local memory store (LMStr): A hardware controlled shared scratchpad for multicores. - Nafiul Alam Siddique; Abdel-Hameed A. Badawy; Jeanine E. Cook; David Resnick (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI, 2017)

The time-varying nature of cache utilization: A case study on the Mantevo and Apex benchmarks. - Nafiul Alam Siddique; Patricia A. Grubel; Abdel-Hameed A. Badawy (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI, 2017)

A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC. - Nafiul Alam Siddique; Patricia Grubel; Abdel-Hameed A. Badawy; Jeanine E. Cook (J. Supercomput., 2018)