A Distortion Compensating Flash Analog-to-Digital Conversion Technique. - Venkata Srinivas; Shanthi Pavan; Ashish Lachhwani; Naga Sasidhar (IEEE J. Solid State Circuits, 2006)

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback. - Naga Sasidhar; Youn-Jae Kook; Seiji Takeuchi; Koichi Hamashita; Kaoru Takasuka; Pavan Kumar Hanumolu; Un-Ku Moon (IEEE J. Solid State Circuits, 2009)

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. - Rajesh Inti; Wenjing Yin; Amr Elshazly; Naga Sasidhar; Pavan Kumar Hanumolu (ISSCC, 2011)

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. - Rajesh Inti; Wenjing Yin; Amr Elshazly; Naga Sasidhar; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2011)

Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping. - Naga Sasidhar; David Gubbins; Pavan Kumar Hanumolu; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2012)