Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. - Lun Ye; Foong-Charn Chang; Peter Feldmann; Rakesh Chadha; Nagaraj Ns; Frank Cano (DATE, 1999)

Performance and Reliability Verification of C6201/C6701 Digital Signal Processors. - Nagaraj Ns; Frank Cano; Sudha Thiruvengadam; Deepak Kapoor (ICCD, 1999)

Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. - Nagaraj Ns; Poras T. Balsara; Cyrus D. Cantrell (VLSI Design, 1999)

Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. - Nagaraj Ns; Poras T. Balsara; Cyrus D. Cantrell (VLSI Design, 2001)

Who solves the variability problem? - Nagaraj Ns; Juan C. Rey; Jamil Kawa; Robert C. Aitken; Christian Lütkemeyer; Vijay Pitchumani; Andrzej J. Strojwas; Steve Trimberger (DAC, 2010)

What's cool for the future of ultra low power designs? - Nagaraj Ns; John Byler; Koorosh Nazifi; Venugopal Puvvada; Toshiyuki Saito; Alan Gibbons; S. Balajee (DAC, 2010)