General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies. - N. Venkateswaran 002; C. Chandramouli (ICES, 2003)

Analysis of Bit Transition Count for EDAC Encoded FSM. - N. Venkateswaran 002; V. Balaji; Venkataraman Mahalingam; T. L. Rajaprabhu (IOLTS, 2003)

Frequency Domain Testing of General Purpose Processors at the Instruction Execution Level. - N. Venkateswaran 002; Krishna Bharath (DELTA, 2004)

Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design. - N. Venkateswaran 002; V. Barath Kumar; R. Raghavan; R. Srinivas; S. Subramanian; V. Balaji; Venkataraman Mahalingam; T. L. Rajaprabhu (DELTA, 2004)

Memory in processor: a novel design paradigm for supercomputing architectures. - Nagarajan Venkateswaran; Aditya Krishnan 002; S. Niranjan Kumar; Arrvindh Shriraman; Srinivas Sridharan (SIGARCH Comput. Archit. News, 2004)

Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance. - Nagarajan Venkateswaran; Arrvindh Shriraman; Niranjan Soundararajan (IPDPS, 2005)

Fault tolerant bus architecture for deep submicron based processors. - N. Venkateswaran 002; S. Balaji; V. Sridhar (SIGARCH Comput. Archit. News, 2005)

PASCOM: Power Model for Supercomputers. - Arrvindh Shriraman; Nagarajan Venkateswaran; Niranjan Soundararajan (ARCS, 2006)

DNA Based Evolutionary Approach for Microprocessor Design Automation. - Nagarajan Venkateswaran; Arjun Kumeresh; Harish Chandran (ICANNGA (1), 2007)

Future generation supercomputers I: a paradigm for node architecture. - Nagarajan Venkateswaran; Deepak Srinivasan; Madhavan Manivannan; T. P. Ramnath Sai Sagar; Shyamsundar Gopalakrishnan; Vinoth Krishnan Elangovan; Karthik Chandrasekar 001; Prem Kumar Ramesh; Viswanath Venkatesan; Arvindakshan Babu; Sudharshan (SIGARCH Comput. Archit. News, 2007)

Future generation supercomputers II: a paradigm for cluster architecture. - Nagarajan Venkateswaran; Deepak Srinivasan; Madhavan Manivannan; T. P. Ramnath Sai Sagar; Shyamsundar Gopalakrishnan; Vinoth Krishnan Elangovan; Arvind M; Prem Kumar Ramesh; Karthik Ganesan 006; Viswanath Krishnamurthy; Sivaramakrishnan (SIGARCH Comput. Archit. News, 2007)

Design for Testability of Functional Cores in High Performance Node Architectures. - Nagarajan Venkateswaran; Karthik Chandrasekar 001; Shrikanth Ganapathy (DELTA, 2008)

On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system. - N. Venkateswaran 002; Vinoth Krishnan Elangovan; Karthik Ganesan 006; TP Ramnath Sai Sagar; Sriram Aananthakrishanan; Shreyas Ramalingam; Shyamsundar Gopalakrishnan; Madhavan Manivannan; Deepak Srinivasan; Viswanath Krishnamurthy; Karthik Chandrasekar 001; Viswanath Venkatesan; et al. (IPDPS, 2008)

A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient. - Nagarajan Venkateswaran; Ravindhiran Mukundrajan; Mrigank Sharma; Badrinarayanan Ravi (ISVLSI, 2009)

Towards modeling and integrated design automation of supercomputing clusters (MIDAS). - Nagarajan Venkateswaran; Aravind Vasudevan; Balaji Subramaniam; Ravindhiran Mukundrajan; T. P. Ramnath Sai Sagar; Madhavan Manivannan; Sriram Murali; Vinoth Krishnan Elangovan (Comput. Sci. Res. Dev., 2009)

Custom Built Heterogeneous Multi-core Architectures (CUBEMACH): Breaking the conventions. - Nagarajan Venkateswaran; Karthikeyan P. Saravanan; Nachiappan Chidambaram Nachiappan; Aravind Vasudevan; Balaji Subramaniam; Ravindhiran Mukundrajan (IPDPS Workshops, 2010)

SCOC IP Cores for Custom Built Supercomputing Nodes. - Nagarajan Venkateswaran; Rajagopal Hariharan; Vinesh Srinivasan; Ram Srivatsa Kannan; Prashanth Thinakaran; Vigneshwaran Sankaran; Bharanidharan Vasudevan; Ravindhiran Mukundrajan; Nachiappan Chidambaram Nachiappan; Aswin Sridharan; Karthikeyan P. Saravanan; Vignesh Adhinarayanan; et al. (ISVLSI, 2012)

Compilation Accelerator on Silicon. - Nagarajan Venkateswaran; Vinesh Srinivasan; Ram Srivatsa Kannan; Prashanth Thinakaran; Rajagopal Hariharan; Bharanidharan Vasudevan; Nachiappan Chidambaram Nachiappan; Karthikeyan P. Saravanan; Aswin Sridharan; Vigneshwaran Sankaran; Vignesh Adhinarayanan; V. S. Vignesh; et al. (ISVLSI, 2012)

Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores. - Nagarajan Venkateswaran; Kartik Lakshminarasimhan; Akash Sridhar; Prashanth Thinakaran; Rajagopal Hariharan; Vinesh Srinivasan; Ram Srivatsa Kannan; Aswin Sridharan (ISVLSI, 2013)