Quasi-complementary BiCMOS for sub-3-V digital circuits. - Kazuo Yano; Mitsuru Hiraki; Shoji Shukuri; Yasuo Onose; Mitsuru Hirao; Nagatoshi Ohki; Takashi Nishida; Koichi Seki; Katsuhiro Shimohigashi (IEEE J. Solid State Circuits, 1991)

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules. - Kazuo Yano; Mitsuru Hiraki; Shoji Shukuri; M. Hanawa; Masato Suzuki; S. Morita; A. Kawamata; Nagatoshi Ohki; Takashi Nishida; Koichi Seki (IEEE J. Solid State Circuits, 1992)

A 16-Mb CMOS SRAM with a 2.3- mu m2 single-bit-line memory cell. - Katsuro Sasaki; Kiyotsugu Ueda; Koichi Takasugi; Hiroshi Toyoshima; Koichiro Ishibashi; Toshiaki Yamanaka; Naotaka Hashimoto; Nagatoshi Ohki (IEEE J. Solid State Circuits, 1993)

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. - Koichiro Ishibashi; Koichi Takasugi; Kunihiro Komiyaji; Hiroshi Toyoshima; Toshiaki Yamanaka; Akira Fukami; Naotaka Hashimoto; Nagatoshi Ohki; Akihiro Shimizu; Takashi Hashimoto; Takahiro Nagano; Takashi Nishida (IEEE J. Solid State Circuits, 1995)

A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. - Koichiro Ishibashi; Kunihiro Komiyaji; Hiroshi Toyoshima; Masataka Minami; Nagatoshi Ohki; Hiroshi Ishida; Toshiaki Yamanaka; Takahiro Nagano; Takashi Nishida (IEEE J. Solid State Circuits, 1995)

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. - Hiroyuki Mizuno; Nozomu Matsuzaki; Kenichi Osada; Toshinobu Shinbo; Nagatoshi Ohki; Hiroshi Ishida; Koichiro Ishibashi; Tokuo Kure (IEEE J. Solid State Circuits, 1996)