A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS. - Nagendra Krishnapura; Peter R. Kinget (IEEE J. Solid State Circuits, 2000)

Noise and power reduction in filters through the use of adjustable biasing. - Nagendra Krishnapura; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2001)

Micropower low-voltage analog filter in a digital CMOS process. - Nagendra Krishnapura; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2003)

A 90μW 15-bit ΔΣ ADC for digital audio. - Shanthi Pavan; Nagendra Krishnapura; Ramalingam Pandarinathan; Prabu Sankar (ESSCIRC, 2007)

Automatic Tuning of Time Constants in Continuous-Time Delta-Sigma Modulators. - Shanthi Pavan; Nagendra Krishnapura (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Oversampling Analog-to-Digital Converter Design. - Shanthi Pavan; Nagendra Krishnapura (VLSI Design, 2008)

A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications. - Shanthi Pavan; Nagendra Krishnapura; Ramalingam Pandarinathan; Prabu Sankar (IEEE J. Solid State Circuits, 2008)

Negative Feedback System and Circuit Design. - Nagendra Krishnapura; Shanthi Pavan (VLSI Design, 2009)

A Comparison of Approaches to Carrier Generation for Zigbee Transceivers. - Leburu Manojkumar; Arun Mohan 003; Nagendra Krishnapura (VLSI Design, 2009)

Efficient determination of feedback DAC errors for digital correction in ΔΣ A/D converters. - Nagendra Krishnapura (ISCAS, 2010)

A 100 µW Decimator for a 16 bit 24 kHz bandwidth Audio ΔΣ Modulator. - Shankar Parameswaran; Nagendra Krishnapura (ISCAS, 2010)

Spur reduction in wideband PLLs by random positioning of charge pump current pulses. - Chembiyan Thambidurai; Nagendra Krishnapura (ISCAS, 2010)

Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators. - Vikas Singh; Nagendra Krishnapura; Shanthi Pavan (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay. - Vikas Singh; Nagendra Krishnapura; Shanthi Pavan; Baradwaj Vigraham; Nimit Nigania; Debasish Behera (CICC, 2011)

Electronic time stretching for fast digitization. - Nagendra Krishnapura (ISCAS, 2011)

A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps. - Nagendra Krishnapura; Abhishek Agrawal; Sameer Singh (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

On Pulse Position Modulation and Its Application to PLLs for Spur Reduction. - Chembiyan Thambidurai; Nagendra Krishnapura (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Introducing negative feedback with an integrator as the central element. - Nagendra Krishnapura (ISCAS, 2012)

Synthesis based introduction to opamps and phase locked loops. - Nagendra Krishnapura (ISCAS, 2012)

A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay. - Vikas Singh; Nagendra Krishnapura; Shanthi Pavan; Baradwaj Vigraham; Debasish Behera; Nimit Nigania (IEEE J. Solid State Circuits, 2012)

A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter. - Debasish Behera; Nagendra Krishnapura (ESSCIRC, 2014)

Tutorial T6A: Pedagogy of Negative Feedback Circuits. - Nagendra Krishnapura (VLSID, 2014)

A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions. - Nagendra Krishnapura; K. S. Rakshitdatta (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Gain enhanced high frequency OTA with on-chip tuned negative conductance load. - Imon Mondal; Nagendra Krishnapura (ISCAS, 2015)

Accurate Constant Transconductance Generation without Off-Chip Components. - Imon Mondal; Nagendra Krishnapura (VLSID, 2015)

On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback. - K. S. Rakshitdatta; Nagendra Krishnapura (VLSID, 2015)

A tail-resonance calibration technique for wide tuning range LC VCOs. - Abhishek Bhat; Nagendra Krishnapura (ISCAS, 2016)

Demystifying Time Varying Circuits and Systems. - Shanthi Pavan; Nagendra Krishnapura (VLSID, 2016)

A 12.5 mW, 11.1 nV√Hz, -115 dB THD, Settling, 18 bit SAR ADC Driver in 0.6 µm CMOS. - K. S. Rakshitdatta; Yujendra Mitikiri; Nagendra Krishnapura (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Session 12-Analog techniques I. - Nagendra Krishnapura; Ken Suyama (CICC, 2017)

Optimum scaling of stages in a frequency divider chain for best jitter FoM. - Sumit Kumar; Nagendra Krishnapura (ISCAS, 2017)

25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS. - Subhashish Mukherjee; Anoop Narayan Bhat; Kumar Anurag Shrivastava; Madhulatha Bonu; Benjamin Sutton; Venugopal Gopinathan; Ganesan Thiagarajan; Abhijit Patki; Jhankar Malakar; Nagendra Krishnapura (ISSCC, 2017)

A Low Power Multi-channel Input Delta-Sigma ADC without Reset. - Ashwin Kumar Siva Kumar; Debasish Behera; Nagendra Krishnapura (VLSID, 2017)

A 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13µm CMOS. - Imon Mondal; Nagendra Krishnapura (IEEE J. Solid State Circuits, 2017)

Linearity- and Gain-Enhanced Wideband Transconductor Using Digitally Auto-Tuned Negative Conductance Load. - Imon Mondal; Nagendra Krishnapura (ISCAS, 2018)

An Automatic LO Leakage Calibration Method for Class-AB Power Mixer Based RF Transmitters. - M. V. Praveen; Nagendra Krishnapura (ISCAS, 2018)

Low 1/f3 Phase Noise Quadrature LC VCOs. - Abhishek Bhat; Nagendra Krishnapura (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion. - R. S. Ashwin Kumar; Debasish Behera; Nagendra Krishnapura (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters. - Imon Mondal; Nagendra Krishnapura (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter. - R. S. Ashwin Kumar; Nagendra Krishnapura (ESSCIRC, 2019)

Static Phase Offset Reduction Technique for Delay Locked Loops. - Chithra; Nagendra Krishnapura (ISCAS, 2019)

A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios. - Abhishek Bhat; Nagendra Krishnapura (ISSCC, 2019)

On-Chip Static Phase Difference Measurement Circuit With Gain and Offset Calibration. - Abhishek Bhat; Nagendra Krishnapura (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables. - Nagendra Krishnapura; Anoop Narayan Bhat; Subhashish Mukherjee; Kumar Anurag Shrivastava; Madhulatha Bonu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs. - Sangeeta Kumar; Rajashekar Goroju; Dileep Kumar Bhat; K. S. Rakshitdatta; Nagendra Krishnapura (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters. - Vipul Bajaj; Anand Kannan; Minkle E. Paul; Nagendra Krishnapura (ISCAS, 2020)

A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process. - Apoorva Bhatia; Yogesh Darwhekar; Subhashish Mukherjee; Samuel Martin; Nagendra Krishnapura (ISCAS, 2020)

A 36dB Gain Range, 0.5dB Gain Step Variable Gain Amplifier with 10 to 25MHz Bandwidth Third-Order Filter for Portable Ultrasound Systems. - Purnendu Bhattaru; Nagendra Krishnapura (VLSID, 2020)

High Linearity Transmit Power Mixers Using Baseband Current Feedback. - M. V. Praveen; Nagendra Krishnapura (IEEE J. Solid State Circuits, 2020)

A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems. - Chithra; Nagendra Krishnapura (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset. - R. S. Ashwin Kumar; Nagendra Krishnapura (IEEE Trans. Circuits Syst., 2020)

Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). - Yun Chiu; Man-Kay Law; Nagendra Krishnapura; Jason T. Stauth; Jeffrey S. Walling (IEEE J. Solid State Circuits, 2021)

Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit. - Chithra; Aditya Narayanan; R. S. Ashwin Kumar; Nagendra Krishnapura (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Effects of AC Response Imperfections in True-Time-Delay Lines. - Imon Mondal; Nagendra Krishnapura (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier. - R. S. Ashwin Kumar; Nagendra Krishnapura; Paramita Banerjee (IEEE J. Solid State Circuits, 2022)

A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched Gm for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs. - Abhishek Bhat; Nagendra Krishnapura (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Multi-Channel Analog-to-Digital Conversion Using a Delta-Sigma Modulator Without Reset and a Modulated-Sinc-Sum Filter. - R. S. Ashwin Kumar; Nagendra Krishnapura (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis. - Sumit Kumar; Nagendra Krishnapura (APCCAS, 2023)

A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur. - Soumith Kusumanchi; Srinivas Theertham; Arpan Thakkar; Nagendra Krishnapura (APCCAS, 2023)

Simulation of Divider Phase Noise and Spurious Tones in Integer-N PLLs. - Aditya Narayanan; Nagendra Krishnapura (ICECS, 2023)

Bandpass Filter and Oscillator ICs with THD ppd for Testing High-Resolution ADCs. - Subha Sarkar; Rajat Agarwal; Nagendra Krishnapura (ISSCC, 2023)

Analysis of Signal Transmission through Time-Varying Inductively Coupled Links. - Nagendra Krishnapura (ISCAS, 2024)

A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays. - Aditya Narayanan; Abhishek Bhat; Nagendra Krishnapura (IEEE J. Solid State Circuits, 2024)

Design Considerations for a Closed-loop Digital Class-D Audio Amplifier. - Ananya Senapati; Nagendra Krishnapura (ISCAS, 2025)

A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver. - Chakravarti Bheemisetti; Karunanidhan Pandey; Idan Lotan; Gadi Ori; Ahmad Khairi; Yoel Krupnik; Udi Virobnik; Subrahmanyam Boyapati; Ariel Cohen 001; Nagendra Krishnapura (IEEE J. Solid State Circuits, 2025)