Understanding performance, power and energy behavior in asymmetric multiprocessors. - Nagesh B. Lakshminarayana; Hyesoon Kim (ICCD, 2008)

Age based scheduling for asymmetric multiprocessors. - Nagesh B. Lakshminarayana; Jaekyu Lee; Hyesoon Kim (SC, 2009)

Many-Thread Aware Prefetching Mechanisms for GPGPU Applications. - Jaekyu Lee; Nagesh B. Lakshminarayana; Hyesoon Kim; Richard W. Vuduc (MICRO, 2010)

DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function. - Nagesh B. Lakshminarayana; Jaekyu Lee; Hyesoon Kim; Jinwoo Shin (IEEE Comput. Archit. Lett., 2012)

SD3: An Efficient Dynamic Data-Dependence Profiling Mechanism. - Minjang Kim; Nagesh B. Lakshminarayana; Hyesoon Kim; Chi-Keung Luk (IEEE Trans. Computers, 2013)

Spare register aware prefetching for graph algorithms on GPUs. - Nagesh B. Lakshminarayana; Hyesoon Kim (HPCA, 2014)

Power Modeling for GPU Architectures Using McPAT. - Jieun Lim 001; Nagesh B. Lakshminarayana; Hyesoon Kim; William J. Song; Sudhakar Yalamanchili; Wonyong Sung (ACM Trans. Design Autom. Electr. Syst., 2014)

Block-Precise Processors: Low-Power Processors with Reduced Operand Store Accesses and Result Broadcasts. - Nagesh B. Lakshminarayana; Hyesoon Kim (IEEE Trans. Computers, 2015)

Efficient graph algorithm execution on data-parallel architectures. - Nagesh B. Lakshminarayana (2015)