Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. - Nagesh Tamarapalli; Janusz Rajski (ITC, 1996)

Automated synthesis of large phase shifters for built-in self-test. - Janusz Rajski; Nagesh Tamarapalli; Jerzy Tyszer (ITC, 1998)

Logic BIST for large industrial designs: real issues and case studies. - Graham Hetherington; Tony Fryars; Nagesh Tamarapalli; Mark Kassab; Abu S. M. Hassan; Janusz Rajski (ITC, 1999)

Automated synthesis of phase shifters for built-in self-testapplications. - Janusz Rajski; Nagesh Tamarapalli; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Embedded Deterministic Test for Low-Cost Manufacturing Test. - Janusz Rajski; Jerzy Tyszer; Mark Kassab; Nilanjan Mukherjee 001; Rob Thompson; Kun-Han Tsai; Andre Hertwig; Nagesh Tamarapalli; Grzegorz Mrugalski; Geir Eide; Jun Qian (ITC, 2002)

Impact of Multiple-Detect Test Patterns on Product Quality. - Brady Benware; Chris Schuermyer; Sreenevasan Ranganathan; Robert Madge; Prabhu Krishnamurthy; Nagesh Tamarapalli; Kun-Han Tsai; Janusz Rajski (ITC, 2003)

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. - Frank Poehl; Matthias Beck; Ralf Arnold; Peter Muhmenthaler; Nagesh Tamarapalli; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2003)

High-Frequency, At-Speed Scan Testing. - Xijiang Lin; Ron Press; Janusz Rajski; Paul Reuter; Thomas Rinderknecht; Bruce Swanson; Nagesh Tamarapalli (IEEE Des. Test Comput., 2003)

Embedded Deterministic Test for Low-Cost Manufacturing. - Janusz Rajski; Mark Kassab; Nilanjan Mukherjee 001; Nagesh Tamarapalli; Jerzy Tyszer; Jun Qian (IEEE Des. Test Comput., 2003)

Compactor Independent Direct Diagnosis. - Wu-Tung Cheng; Kun-Han Tsai; Yu Huang 005; Nagesh Tamarapalli; Janusz Rajski (Asian Test Symposium, 2004)

Compression mode diagnosis enables high volume monitoring diagnosis flow. - Andreas Leininger; Peter Muhmenthaler; Wu-Tung Cheng; Nagesh Tamarapalli; Wu Yang; Kun-Han Hans Tsai (ITC, 2005)

Achieving higher yield through diagnosis. - Nagesh Tamarapalli (ITC, 2005)

The Next Step in Volume Scan Diagnosis: Standard Fail Data Format. - Andreas Leininger; Ajay Khoche; Martin Fischer 002; Nagesh Tamarapalli; Wu-Tung Cheng; Randy Klingenberg; Wu Yang (ATS, 2006)

Diagnosis with Limited Failure Information. - Yu Huang 005; Wu-Tung Cheng; Nagesh Tamarapalli; Janusz Rajski; Randy Klingenberg; Will Hsu; Yuan-Shih Chen (ITC, 2006)

A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. - Martin Keim; Nagesh Tamarapalli; Huaxing Tang; Manish Sharma; Janusz Rajski; Chris Schuermyer; Brady Benware (ITC, 2006)

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. - Nandu Tendolkar; Dawit Belete; Bill Schwarz; Bob Podnar; Akshay Gupta; Steve Karako; Wu-Tung Cheng; Alex Babin; Kun-Han Tsai; Nagesh Tamarapalli; Greg Aldrich (ITC, 2006)

DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. - David Abercrombie; Bernd Koenemann; Nagesh Tamarapalli; Srikanth Venkataraman (VLSI Design, 2006)

DFM / DFT / SiliconDebug / Diagnosis. - Srikanth Venkataraman; Nagesh Tamarapalli (VLSI Design, 2008)

Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield. - Srikanth Venkataraman; Nagesh Tamarapalli (VLSI Design, 2012)

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. - Prabhat Mishra 001; Masahiro Fujita; Virendra Singh; Nagesh Tamarapalli; Sharad Kumar; Rajesh Mittal (VLSI Design, 2013)

Application of Test-View Modeling to Hierarchical ATPG. - Rahul Shukla; Phong Loi; Ken Pham; Arie Margulis; Kathy Yang; Nagesh Tamarapalli (VLSID, 2014)

Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test. - Nagesh Tamarapalli; Prashanth Vallur; Sachin Kulkarni (VLSID, 2015)