High-Speed Logic Simulation on Vector Processors. - Nagisa Ishiura; Hiroto Yasuura; Shuzo Yajima (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits. - Nagisa Ishiura; Mizuki Takahashi; Shuzo Yajima (DAC, 1989)

Semantics of a Hardware Design Language for Japanese Standardization. - Hiroto Yasuura; Nagisa Ishiura (DAC, 1989)

Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram. - Nagisa Ishiura; Yutaka Deguchi; Shuzo Yajima (DAC, 1990)

NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. - Nagisa Ishiura; Hiroto Yasuura; Shuzo Yajima (DAC, 1990)

Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. - Shin-ichi Minato; Nagisa Ishiura; Shuzo Yajima (DAC, 1990)

Formal semantics of UDL/I and its applications to CAD/DA tools. - Hiroto Yasuura; Nagisa Ishiura (ICCD, 1990)

Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor. - Nagisa Ishiura; Masayuki Ito; Shuzo Yajima (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits. - Yutaka Deguchi; Nagisa Ishiura; Shuzo Yajima (DAC, 1991)

Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. - Hiroyuki Ochi; Nagisa Ishiura; Shuzo Yajima (DAC, 1991)

Minimazation of Binary Decision Diagrams Based on Exchanges of Variables. - Nagisa Ishiura; Hiroshi Sawada; Shuzo Yajima (ICCAD, 1991)

Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets. - Noriyuki Takahashi; Nagisa Ishiura; Shuzo Yajima (ICCAD, 1991)

Linear time fault simulation algorithm using a content addressable memory. - Nagisa Ishiura; Shuzo Yajima (EURO-DAC, 1992)

Fault simulation for multiple faults by Boolean function manipulation. - Noriyuki Takahashi; Nagisa Ishiura; Shuzo Yajima (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Optimal Scheduling for Conditional Recource Sharing. - Akihisa Yamada 001; Satoru Nakamura; Nagisa Ishiura; Isao Shirakawa; Takashi Kambe (ISCAS, 1995)

Binding and Scheduling Algorithms for Highly Retargetable Compilation. - Masayuki Yamaguchi; Nagisa Ishiura; Takashi Kambe (ASP-DAC, 1998)

Thread partitioning method for hardware compiler bach. - Mizuki Takahashi; Nagisa Ishiura; Akihisa Yamada 001; Takashi Kambe (ASP-DAC, 2000)

Datapath oriented codesign method of application specific DSPs using retargetable compiler. - Nagisa Ishiura; Tatsuo Watanabe (APCCAS (1), 2002)

Special Section on VLSI Design and CAD Algorithms. - Nagisa Ishiura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

High-Level Synthesis of Software Function Calls. - Masanari Nishimura; Nagisa Ishiura; Yoshiyuki Ishimori; Hiroyuki Kanbara; Hiroyuki Tomiyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). - Masaharu Imai; Yoshinori Takeuchi; Keishi Sakanushi; Nagisa Ishiura (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors. - Takahiro Kumura; Soichiro Taga; Nagisa Ishiura; Yoshinori Takeuchi; Masaharu Imai (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions. - Eriko Nagai; Atsushi Hashimoto 005; Nagisa Ishiura (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Random testing of C compilers based on test program generation by equivalence transformation. - Kazuhiro Nakamura; Nagisa Ishiura (APCCAS, 2016)

Reverse Engineering from Mainframe Assembly to C Codes in Legacy Migration. - Daisuke Fujiwara; Nagisa Ishiura; Ryo Sakai; Ryo Aoki; Takashi Ogawara (IIAI-AAI, 2016)

Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent Programs. - Atsushi Hashimoto 005; Nagisa Ishiura (IPSJ Trans. Syst. LSI Des. Methodol., 2016)

Distributed memory architecture for high-level synthesis of embedded controllers from Erlang. - Kagumi Azuma; Nagisa Ishiura; Nobuaki Yoshida; Hiroyuki Kanbara (Erlang Workshop, 2017)

Binary synthesis implementing external interrupt handler as independent module. - Naoya Ito; Yuuki Oosako; Nagisa Ishiura; Hiroyuki Kanbara; Hiroyuki Tomiyama (RSP, 2017)

Speculative execution in distributed controllers for high-level synthesis. - Miho Shimizu; Nagisa Ishiura; Sayuri Ota; Wakako Nakano (RSP, 2017)

CF3: Test Suite for Arithmetic Optimization of C Compilers. - Yusuke Hibino; Hirofumi Ikeo; Nagisa Ishiura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Synthesis of Full Hardware Implementation of RTOS-Based Systems. - Yuuki Oosako; Nagisa Ishiura; Hiroyuki Tomiyama; Hiroyuki Kanbara (RSP, 2018)

Random testing of compilers' performance based on mixed static and dynamic code comparison. - Kota Kitaura; Nagisa Ishiura (A-TEST@ESEC/SIGSOFT FSE, 2018)

Extending equivalence transformation based program generator for random testing of C compilers. - Shogo Takakura; Mitsuyoshi Iwatsuji; Nagisa Ishiura (A-TEST@ESEC/SIGSOFT FSE, 2018)

Full Hardware Implementation of FreeRTOS-Based Real-Time Systems. - Wakako Nakano; Yukino Shinohara; Nagisa Ishiura (TENCON, 2021)

Enumeration of Genaralized Parallel Counters for Multi-Input Adder Synthesis for FPGAs. - Mugi Noda; Nagisa Ishiura (APCCAS, 2024)