Constraint Allocation in Analog System Synthesis. - Nagu R. Dhanwada; Ranga Vemuri (VLSI Design, 1998)

Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. - Nagu R. Dhanwada; Adrián Núñez-Aldana; Ranga Vemuri (ASP-DAC, 1999)

Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. - Alex Doboli; Adrián Núñez-Aldana; Nagu R. Dhanwada; Sree Ganesan; Ranga Vemuri (DAC, 1999)

Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. - Nagu R. Dhanwada; Adrián Núñez-Aldana; Ranga Vemuri (DATE, 1999)

A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis. - Nagu R. Dhanwada; Adrián Núñez-Aldana; Ranga Vemuri (ISCAS (6), 1999)

Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. - Nagu R. Dhanwada; Adrián Núñez-Aldana; Ranga Vemuri (VLSI Design, 1999)

A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems. - Alex Doboli; Nagu R. Dhanwada; Ranga Vemuri (ISCAS, 2000)

SEAS: a system for early analysis of SoCs. - Reinaldo A. Bergamaschi; Youngsoo Shin; Nagu R. Dhanwada; Subhrajit Bhattacharya; William E. Dougherty; Indira Nair; John A. Darringer; Sarala Paliwal (CODES+ISSS, 2003)

Design topology aware physical metrics for placement analysis. - Shyam Ramji; Nagu R. Dhanwada (ACM Great Lakes Symposium on VLSI, 2003)

Architecting voltage islands in core-based system-on-a-chip designs. - Jingcao Hu; Youngsoo Shin; Nagu R. Dhanwada; Radu Marculescu (ISLPED, 2004)

A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. - Alex Doboli; Nagu R. Dhanwada; Adrián Núñez-Aldana; Ranga Vemuri (ACM Trans. Design Autom. Electr. Syst., 2004)

A power estimation methodology for systemC transaction level models. - Nagu R. Dhanwada; Ing-Chao Lin; Vijaykrishnan Narayanan (CODES+ISSS, 2005)

Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. - Wei-Lun Hung; Greg M. Link; Yuan Xie 001; Narayanan Vijaykrishnan; Nagu R. Dhanwada; John Conner (ICCD, 2005)

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems. - Nagu R. Dhanwada; Reinaldo A. Bergamaschi; William W. Dungan; Indira Nair; Paul Gramann; William E. Dougherty; Ing-Chao Lin (Des. Autom. Embed. Syst., 2005)

Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. - Ing-Chao Lin; Suresh Srinivasan; Narayanan Vijaykrishnan; Nagu R. Dhanwada (ISQED, 2006)

Hierarchical constraint transformation based on genetic optimization for analog system synthesis. - Nagu R. Dhanwada; Alex Doboli; Adrián Núñez-Aldana; Ranga Vemuri (Integr., 2006)

Performance modeling for early analysis of multi-core systems. - Reinaldo A. Bergamaschi; Indira Nair; Gero Dittmann; Hiren D. Patel; Geert Janssen; Nagu R. Dhanwada; Alper Buyuktosunoglu; Emrah Acar; Gi-Joon Nam; Dorothy Kucar; Pradip Bose; John A. Darringer; et al. (CODES+ISSS, 2007)

Exploring power management in multi-core systems. - Reinaldo A. Bergamaschi; Guoling Han; Alper Buyuktosunoglu; Hiren D. Patel; Indira Nair; Gero Dittmann; Geert Janssen; Nagu R. Dhanwada; Zhigang Hu; Pradip Bose; John A. Darringer (ASP-DAC, 2008)

Leakage Power Contributor Modeling. - Nagu R. Dhanwada; David J. Hathaway; Jerry Frenkil; W. Rhett Davis; Harun Demircioglu (IEEE Des. Test Comput., 2012)

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. - Nagu R. Dhanwada; David J. Hathaway; Victor V. Zyuban; Peng Peng; Karl Moody; William W. Dungan; Arun Joseph; Rahul M. Rao; Christopher J. Gonzalez (ICCAD, 2013)

Towards a standard flow for system level power modeling. - Nagu R. Dhanwada; William Rhett Davis; Jerry Frenkil (ICCAD, 2014)

Process Synchronization in Multi-core Systems Using On-Chip Memories. - Arun Joseph; Nagu R. Dhanwada (VLSID, 2014)

Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis. - Arun Joseph; Spandana Rachamalla; Shashidhar Reddy; Nagu R. Dhanwada (VLSID, 2019)

Energy Efficiency Boost in the AI-Infused POWER10 Processor. - Brian W. Thompto; Dung Q. Nguyen; José E. Moreira; Ramon Bertran; Hans M. Jacobson; Richard J. Eickemeyer; Rahul M. Rao; Michael Goulet; Marcy Byers; Christopher J. Gonzalez; Karthik Swaminathan; Nagu R. Dhanwada; et al. (ISCA, 2021)