A low power programmable FIR filter using sharing multiplication technique. - Nahla T. Abou-El-Kheir; Moataz S. El-Kharashi; Magdy A. El-Moursy (ICICDT, 2012)

An adaptive digital background calibration technique using variable step size LMS for pipelined ADC. - Nahla T. Abou-El-Kheir; Mohamed Abbas; Mohamed Essam Khedr (CSNDSP, 2014)

A fast power efficient equalization-based digital background calibration technique for pipelined ADC. - Nahla T. Abou-El-Kheir; Mohamed Essam Khedr; Mohamed Abbas (MIXDES, 2014)

High performance interpolation filter using direct computation. - Ratshih S. Abd El-Azeem; Magdy A. El-Moursy; Amin M. Nassar; Ahmed Gharib; Nahla T. Abou-El-Kheir; Moataz S. El-Kharashi (IDT, 2016)

Direct computation for high performance interpolation filter. - Ratshih S. Abd El-Azeem; Magdy A. El-Moursy; Amin M. Nassar; Ahmed Gharib; Nahla T. Abou-El-Kheir; Moataz S. El-Kharashi (Microelectron. J., 2016)

A 65 nm Compact High Performance Fully Synthesizable Clock Multiplier Based on an Injection Locked Ring Oscillator. - Nahla T. Abou-El-Kheir; Ralph D. Mason; Mingze Li; Mustapha C. E. Yagoub (ISCAS, 2018)

A High-Performance Low Complexity All-Digital Fractional Clock Multiplier. - Nahla T. Abou-El-Kheir; Ralph D. Mason; Mingze Li; Mustapha C. E. Yagoub (A-SSCC, 2019)

A sub-harmonic injection locking clock multiplier with FLL PVT calibrator. - Nahla T. Abou-El-Kheir; Ralph D. Mason; Mingze Li; Mustapha C. E. Yagoub (Microelectron. J., 2020)