A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement. - Nai-Chen Daniel Cheng; Yu Lee; Ji-Jan Chen (ATS, 2007)

Experimental Results of Built-In Jitter Measurement for Gigahertz Clock. - Nai-Chen Daniel Cheng; Yu Lee; Ji-Jan Chen (ATS, 2008)

An embedded wide-range and high-resolution CLOCK jitter measurement circuit. - Yu Lee; Ching-Yuan Yang; Nai-Chen Daniel Cheng; Ji-Jan Chen (DATE, 2010)

A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS. - Chih-Hsiang Chang; Ching-Yuan Yang; Yu Lee; Jun-Hong Weng; Nai-Chen Cheng 001 (ESSCIRC, 2013)

A 32.4 μW RF front end for 2.4 GHz wake-up receiver. - Yu-Lin Tsou; Nai-Chen Daniel Cheng; Christina F. Jou (ISCAS, 2013)

Invited - Wireless sensor nodes for environmental monitoring in internet of things. - Ting-Chou Lu; Li-Ren Huang; Yu Lee; Kun-Ju Tsai; Yu-Te Liao; Nai-Chen Cheng 001; Yuan-Hua Chu; Yi-Hsing Tsai; Fang-Chu Chen; Tzi-cker Chiueh (DAC, 2016)

A 0.8V, 43.5μW ECG signal acquisition IC with a referenceless time-to-digital converter. - Shu-Hsuan Lin; Fu-To Lin; Nai-Chen Cheng 001; Yu-Te Liao (ISCAS, 2016)

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Tze-Chiang Huang; Wen-Hung Huang; Kate Huang; Yu-Chi Chen; Alex Liu; Yu-Jie Huang; Jimmy Wang; Shu-Chun Yang; Nai-Chen Cheng 001; et al. (VLSI Technology and Circuits, 2024)

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Wei-Chih Chen; Wen-Hung Huang; Yu-Chi Chen; Yu-Jie Huang; Alan J. Drake; Chin-Hua Wen; Paul Ranucci; Hsin-Hung Kuo; Aidong Yin; et al. (ISSCC, 2025)