VLSI Implementation of Multi-Channel ECG Lossless Compression System. - Tsung-Han Tsai 001; Nai-Chieh Tung; Ding-Bang Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Hardware architecture design for real-time SIFT extraction with reduced memory usage. - Tsung-Han Tsai 001; Ruizhi Wang; Nai-Chieh Tung (Multim. Tools Appl., 2024)

An FPGA-Based Reconfigurable Convolutional Neural Network Accelerator for Tiny YOLO-V3. - Tsung-Han Tsai 001; Nai-Chieh Tung; Chun-Yu Chen (Circuits Syst. Signal Process., 2025)