An 830mW, 586kbps 1024-bit RSA chip design. - Chingwei Yeh; En-Feng Hsu; Kai-Wen Cheng; Jinn-Shyan Wang; Nai-Jen Chang (DATE Designers' Forum, 2006)

Reverse logistics activities, the task environment, and performance: Taiwanese 3C retailers. - Yi-Chun Huang; Yen-Chun Jim Wu; Nai-Jen Chang; Nolan Boulanger (SOLI, 2010)