Using CoDeL to Rapidly Prototype Network Processsor Extensions. - Nainesh Agarwal; Nikitas J. Dimopoulos (SAMOS, 2004)

Power efficient rapid hardware development using CoDel and automated clock gating. - Nainesh Agarwal; Nikitas J. Dimopoulos (ISCAS, 2006)

Efficient Automated Clock Gating Using CoDeL. - Nainesh Agarwal; Nikitas J. Dimopoulos (SAMOS, 2006)

Towards Automated Power Gating of Registers using CoDeL. - Nainesh Agarwal; Nikitas J. Dimopoulos (ISCAS, 2007)

DSPstone Benchmark of CoDeL's Automated Clock Gating Platform. - Nainesh Agarwal; Nikitas J. Dimopoulos (ISVLSI, 2007)

Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction. - Nainesh Agarwal; Nikitas J. Dimopoulos (SAMOS, 2007)

FSMD partitioning for low power using simulated annealing. - Nainesh Agarwal; Nikitas J. Dimopoulos (ISCAS, 2008)

FSMD Partitioning for Low Power Using ILP. - Nainesh Agarwal; Nikitas J. Dimopoulos (ISVLSI, 2008)

Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing. - Nainesh Agarwal; Nikitas J. Dimopoulos (SAMOS, 2009)

Detecting Broad Length Algorithmically Generated Domains. - Aashna Ahluwalia; Issa Traoré; Karim Ganame; Nainesh Agarwal (ISDDC, 2017)