A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration. - Changsik Yoo; Kye-Hyun Kyung; Kyunam Lim; Hi-Choon Lee; Joon-Wan Chai; Nak-Won Heo; Dong-Jin Lee; Chang-Hyun Kim (IEEE J. Solid State Circuits, 2004)