High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. - S. Kala; Nalesh Sivanandan; Arka Maity; S. K. Nandy 001; Ranjani Narayan (ISCAS, 2013)

Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. - S. Kala; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (ISED, 2014)

Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. - Kavitha T. Madhu; Saptarsi Das; Madhava Krishna C; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (ICSAMOS, 2014)

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. - Saptarsi Das; Kavitha T. Madhu; Madhav Krishna; Nalesh Sivanandan; Farhad Merchant; Santhi Natarajan; Ipsita Biswas; Adithya Pulli; S. K. Nandy 001; Ranjani Narayan (J. Syst. Archit., 2014)

Compiling HPC Kernels for the REDEFINE CGRA. - Kavitha T. Madhu; Saptarsi Das; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (HPCC/CSS/ICESS, 2015)

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. - Nalesh Sivanandan; Kavitha T. Madhu; Saptarsi Das; S. K. Nandy 001; Ranjani Narayan (iNIS, 2015)

Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. - Farhad Merchant; Arka Maity; Mahesh Mahadurkar; Kapil Vatwani; Ishan Munje; Madhava Krishna C; Nalesh Sivanandan; Nandhini Gopalan; Soumyendu Raha; S. K. Nandy 001; Ranjani Narayan (VLSID, 2015)

Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. - S. Kala; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (J. Low Power Electron., 2015)

RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. - Saptarsi Das; Nalesh Sivanandan; Kavitha T. Madhu; Soumitra Kumar Nandy; Ranjani Narayan (VLSID, 2016)

Energy aware synthesis of application kernels through composition of data-paths on a CGRA. - Nalesh Sivanandan; Kavitha T. Madhu; Saptarsi Das; S. K. Nandy 001; Ranjani Narayan (Integr., 2017)

Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering. - S. Kala; Nalesh Sivanandan; Babita R. Jose; Jimson Mathew; Marco Ottavi (DTIS, 2018)

Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA. - S. Kala; Debdeep Paul; Babita R. Jose; Nalesh Sivanandan (ISED, 2018)

A Hardware Architecture for Radial Basis Function Neural Network Classifier. - Mahnaz Mohammadi; Akhil Krishna; Nalesh Sivanandan; S. K. Nandy 001 (IEEE Trans. Parallel Distributed Syst., 2018)

Efficient Hardware Acceleration of Convolutional Neural Networks. - S. Kala; Babita R. Jose; Jimson Mathew; Nalesh Sivanandan (SoCC, 2019)

UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs. - S. Kala; Jimson Mathew; Babita R. Jose; Nalesh Sivanandan (VLSID, 2019)

Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme. - S. Kala; Jimson Mathew; Babita R. Jose; Nalesh Sivanandan (IET Comput. Digit. Tech., 2019)

High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture. - S. Kala; Babita R. Jose; Jimson Mathew; Nalesh Sivanandan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Fast Booth Multipliers Using Approximate 4: 2 Compressors. - S. Sreeparvathy; Rachana George; Rose Mary Kuruvithadam; Nalesh S 001 (iSES, 2021)

Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA. - Mahesh M; Nalesh S 001; S. Kala (SoCC, 2021)

A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA. - Abi K. Krishnan; M. H. Supriya; Nalesh Sivanandan (VDAT, 2021)

Hardware Acceleration of SpMV Multiplier for Deep Learning. - Mahesh Mahadurkar; Nalesh Sivanandan; S. Kala (VDAT, 2021)

Adiabatic Physical Unclonable Function Using Cross-Coupled Pair. - Vishnu Bajjuri; Nalesh S 001; Sree Ranjani Rajendran; S. Kala (iSES, 2022)

Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA. - Noble G; Nalesh S 001; S. Kala (APCCAS, 2023)

Approximate CNN on FPGA Using Toom-Cook Multiplier. - Abhinav Kalvacherla; Rachana George; Nalesh S 001; S. Kala (iSES, 2023)

MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles. - Noble G; Nalesh S 001; S. Kala (VLSID, 2023)

A physically unclonable function architecture with multiple responses on FPGA. - M. A. Muneeb; Nalesh S 001; S. Kala (Int. J. Embed. Syst., 2023)

Implementation and Analysis of Sparse DNN on GPU. - Aparna Nair M. K; Nandhu Sam; Minu A Pillai; Nalesh S 001; Kala S (iSES, 2024)