Hardware-efficient approximate logarithmic division with improved accuracy. - Chitlu Subhasri; Bhaskara Rao Jammu 001; L. Guna Sekhar Sai Harsha; Nalini Bodasingi; Visweswara Rao Samoju (Int. J. Circuit Theory Appl., 2021)

A Low Error, Hardware Efficient Logarithmic Multiplier. - L. Guna Sekhar Sai Harsha; Bhaskara Rao Jammu 001; Nalini Bodasingi; Sreehari Veeramachaneni; Noor Mohammad S. (Circuits Syst. Signal Process., 2022)

Automatic diagnosis of pneumonia using backward elimination method based SVM and its hardware implementation. - Nalini Bodasingi; Balaji Narayanam; Bhaskara Rao Jammu 001 (Int. J. Imaging Syst. Technol., 2022)

Hardware efficient circuit for low error logarithmic converter. - Bhaskara Rao Jammu 001; L. Guna Sekhar Sai Harsha; Nalini Bodasingi; Sreehari Veeramachaneni; Noor Mohammad S. (J. Comput. Methods Sci. Eng., 2022)