MemMON: run-time off-chip detection for memory access violation in embedded systems. - Nam Ho; Anh-Vu Dinh-Duc (SoICT, 2010)

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. - Nam Ho; Paul Kaufmann; Marco Platzner (FPL, 2014)

Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. - Nam Ho; Paul Kaufmann; Marco Platzner (ICES, 2014)

Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. - Nam Ho; Abdullah Fathi Ahmed; Paul Kaufmann; Marco Platzner (AHS, 2015)

Enhancing an x86_64 multi-core architecture with data-flow execution support. - Nam Ho; Andrea Mondelli; Alberto Scionti; Marco Solinas; Antoni Portero; Roberto Giorgi (Conf. Computing Frontiers, 2015)

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions. - Andrea Mondelli; Nam Ho; Alberto Scionti; Marco Solinas; Antoni Portero; Roberto Giorgi (DSD, 2015)

Evaluation methodology for complex non-deterministic functions: A case study in metaheuristic optimization of caches. - Paul Kaufmann; Nam Ho; Marco Platzner (AHS, 2017)

Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor. - Nam Ho; Ishraq Ibne Ashraf; Paul Kaufmann; Marco Platzner (DATE, 2017)

Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. - Nam Ho; Paul Kaufmann; Marco Platzner (FPT, 2017)

FPGA-based reconfigurable cache mapping schemes: design and optimization. - Nam Ho (2018)

Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor. - Nam Ho; Paul Kaufmann; Marco Platzner (SoCPaR, 2019)

Evolution of application-specific cache mappings. - Nam Ho; Paul Kaufmann; Marco Platzner (Int. J. Hybrid Intell. Syst., 2020)

Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors. - Adrià Armejach; Bine Brank; Jordi Cortina; François Dolique; Timothy Hayes 001; Nam Ho; Pierre-Axel Lagadec; Romain Lemaire; Guillem López-Paradís; Laurent Marliac; Miquel Moretó; Pedro Marcuello; et al. (DATE, 2021)

Multilevel simulation-based co-design of next generation HPC microprocessors. - Lilia Zaourar; Mohamed Benazouz; Ayoub Mouhagir; Fatma Jebali; Tanguy Sassolas; Jean-Christophe Weill; Carlos Falquez; Nam Ho; Dirk Pleiter; Antoni Portero; Estela Suarez; Polydoros Petrakis; et al. (PMBS, 2021)

COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores. - Antoni Portero; Carlos Falquez; Nam Ho; Polydoros Petrakis; Stepan Nassyr; Manolis Marazakis; Romain Dolbeau; Jorge Alejandro Nocua Cifuentes; Luis Bertran Alvarez; Dirk Pleiter; Estela Suarez (ARCS, 2023)

Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPC. - Lilia Zaourar; Mohamed Benazouz; Ayoub Mouhagir; Carlos Falquez; Antoni Portero; Nam Ho; Estela Suarez; Polydoros Petrakis; Manolis Marazakis; Francesco Sgherzi; Ivan Fernandez; Romain Dolbeau; et al. (ARCS, 2024)

Data Prefetching on Processors with Heterogeneous Memory. - Berk Saglam; Nam Ho; Carlos Falquez; Antoni Portero; Fabian Schätzle; Estela Suarez; Dirk Pleiter (MEMSYS, 2024)

Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation. - Fabian Schätzle; Carlos Falquez; Stefan Heinen; Nam Ho; Antoni Portero; Estela Suarez; Johannes Van Den Boom; Stefan van Waasen (RAPIDO@HiPEAC, 2024)

Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design. - Fabian Schätzle; Carlos Falquez; Nam Ho; André Zambanini; Johannes Van Den Boom; Estela Suarez (ISC, 2025)

Memory Prefetching Evaluation of Scientific Applications on a Modern HPC Arm-Based Processor. - Nam Ho; Carlos Falquez; Antoni Portero; Estela Suarez; Dirk Pleiter (IEEE Access, 2025)