Degradation of pMOSFETs due to hot electron induced punchthrough. - Donghee Son; Gang-Jun Kim; Ji-Hoon Seo; Nam-Hyun Lee; YongHa Kang; Bongkoo Kang (Microelectron. Reliab., 2016)

Channel width dependence of AC stress on bulk nMOSFETs. - Donghee Son; Gang-Jun Kim; Ji-Hoon Seo; Nam-Hyun Lee; YongHa Kang; Bongkoo Kang (Microelectron. Reliab., 2016)

Effect of OFF-state stress on reliability of nMOSFET in SWD circuits of DRAM. - Jongkyun Kim; Namhyun Lee; Gang-Jun Kim; Young-Yun Lee; Jung-Eun Seok; Yunsung Lee (Microelectron. Reliab., 2018)

Effect of DC/AC stress on the reliability of cell capacitor in DRAM. - Gang-Jun Kim; Nam-Hyun Lee; Jongkyun Kim; Jung Eun Seok; Yunsung Lee (Microelectron. Reliab., 2018)

Comprehensive Study for OFF-State Hot Carrier Degrdation of Scaled nMOSFETs in DRAM. - Nam-Hyun Lee; Jongkyun Kim; Donghee Son; Kangjun Kim; Jung Eun Seok (IRPS, 2019)

The Characterization of Degradation on various SiON pMOSFET transistors under AC/DC NBTI stress. - Gang-Jun Kim; Moonjee Yoon; SungHwan Kim; Myeongkyu Eo; Shinhyung Kim; Taehun You; Namhyun Lee; Kijin Kim; Sangwoo Pae (IRPS, 2021)

Effect of High Temperature on Recovery of Hot Carrier Degradation of scaled nMOSFETs in DRAM. - Donghee Son; Gang-Jun Kim; Jongkyun Kim; Nam-Hyun Lee; Kijin Kim; Sangwoo Pae (IRPS, 2021)

Transistor Reliability Characterization for Advanced DRAM with HK+MG & EUV process technology. - Nam-Hyun Lee; Sunhang Lee; S.-H. Kim; G.-J. Kim; K. W. Lee; Y. S. Lee; Y. C. Hwang; H. S. Kim; S. Pae (IRPS, 2022)

Effect of Off-State Stress on Data-Valid Window Margin for Advanced DRAM Using HK/MG Process Technology. - Sunhang Lee; Nam-Hyun Lee; G.-J. Kim; J. Ahn; Ik-Hwan Kim; S. Ha; S. Rhee; GH Bae; KW Lee; YS Lee; SB. Ko; S. Pae (IRPS, 2024)

Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning. - Jun Hui Park; Jung Nam Kim; Seonhaeng Lee; Gang-Jun Kim; Namhyun Lee; Rock-Hyun Baek; Dae Hwan Kim; Changhyun Kim; Myounggon Kang; Yoon Kim (IEEE Access, 2024)

Cryogenic Body Bias Effect in DRAM Peripheral and Buried-Channel-Array Transistor for Quantum Computing Applications. - Hyunseo You; Kihoon Nam; Jehyun An; Chanyang Park; Donghyun Kim; Seonhaeng Lee; Namhyun Lee; Rock-Hyun Baek (IEEE Access, 2024)

Reliability Characterization Using Accelerated Methods of 1Tb 9th-Gen VNAND for TLC/QLC applications. - Gang-Jun Kim; Taehun You; Sewon Jeon; Seung Hwan Kwak; Hwangju Song; Shinhyung Kim; Nam-Jae Kim; Jaeyeop Ahn; Hyuk Park 006; Seonhaeng Lee; Nam-Hyun Lee; Young Hoon Cho; et al. (IRPS, 2025)