Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks. - Hyunmyung Oh; Hyungjun Kim; Nameun Kang; Yulhwa Kim; Jihoon Park; Jae-Joon Kim (AICAS, 2021)

TAIM: ternary activation in-memory computing hardware with 6T SRAM array. - Nameun Kang; Hyungjun Kim; Hyunmyung Oh; Jae-Joon Kim (DAC, 2022)

In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time. - Inhwan Lee; Eunhwan Kim; Nameun Kang; Hyunmyung Oh; Jae-Joon Kim (DAC, 2023)

A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range. - Eunhwan Kim; Hyunmyung Oh; Nameun Kang; Jihoon Park; Jae-Joon Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2023)