A Triple-Push Voltage Controlled Oscillator in 0.13-µm RFCMOS Technology Operating Near 177GHz. - Namhyung Kim; Kyungmin Kim; Jae-Sung Rieh (IEICE Trans. Electron., 2014)

Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. - Namhyung Kim; Junwhan Ahn; Woong Seo; Kiyoung Choi (VLSI-SoC, 2015)

Exploration of trade-offs in the design of volatile STT-RAM cache. - Namhyung Kim; Kiyoung Choi (J. Syst. Archit., 2016)

Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems. - Namhyung Kim; Junwhan Ahn; Kiyoung Choi; Daniel Sánchez 003; Donghoon Yoo; Soojung Ryu (ACM Trans. Archit. Code Optim., 2018)

Acceleration of DNN Backward Propagation by Selective Computation of Gradients. - Gunhee Lee; Hanmin Park; Namhyung Kim; Joonsang Yu; Sujeong Jo; Kiyoung Choi (DAC, 2019)

NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces. - Changmin Lee 004; Wonjae Shin; Dae Jeong Kim; Yongjun Yu; Sung-Joon Kim; Taekyeong Ko; Deokho Seo; Jongmin Park; Kwanghee Lee; Seongho Choi 002; Namhyung Kim; Vishak G; et al. (HPCA, 2020)

Making a Better Use of Caches for GCN Accelerators with Feature Slicing and Automatic Tile Morphing. - Mingi Yoo; Jaeyong Song; Jounghoo Lee; Namhyung Kim; Youngsok Kim; Jinho Lee (IEEE Comput. Archit. Lett., 2021)

Slice-and-Forge: Making Better Use of Caches for Graph Convolutional Network Accelerators. - Mingi Yoo; Jaeyong Song; Hyeyoon Lee; Jounghoo Lee; Namhyung Kim; Youngsok Kim; Jinho Lee (PACT, 2022)

ComPreEND: Computation Pruning through Predictive Early Negative Detection for ReLU in a Deep Neural Network Accelerator. - Namhyung Kim; Hanmin Park; Dongwoo Lee; Sungbum Kang; Jinho Lee; Kiyoung Choi (IEEE Trans. Computers, 2022)

SGCN: Exploiting Compressed-Sparse Features in Deep Graph Convolutional Network Accelerators. - Mingi Yoo; Jaeyong Song; Jounghoo Lee; Namhyung Kim; Youngsok Kim; Jinho Lee (HPCA, 2023)