Low Power BIST with Smoother and Scan-Chain Reorder . - Nan-Cheng Lai; Sying-Jyan Wang; Yu-Hsuan Fu (Asian Test Symposium, 2004)

Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. - Nan-Cheng Lai; Sying-Jyan Wang; Y.-H. Fu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs. - Nan-Cheng Lai; Sying-Jyan Wang (ATS, 2007)

On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests. - Nan-Cheng Lai; Sying-Jyan Wang (ATS, 2008)

Delay Test with Embedded Test Pattern Generator. - Nan-Cheng Lai; Sying-Jyan Wang (J. Inf. Sci. Eng., 2013)