An optimal probe testing algorithm for the connectivity verification of MCM substrates. - So-Zen Yao; Nan-Chi Chou; Chung-Kuan Cheng; T. C. Hu (ICCAD, 1992)

Performance-driven partitioning using retiming and replication. - Lung-Tien Liu; Minshine Shih; Nan-Chi Chou; Chung-Kuan Cheng; Walter H. Ku (ICCAD, 1993)

Circuit Partitioning for Huge Logic Emulation Systems. - Nan-Chi Chou; Lung-Tien Liu; Chung-Kuan Cheng; Wei-Jin Dai; Rodney Lindelof (DAC, 1994)

A multi-probe approach for MCM substrate testing. - So-Zen Yao; Nan-Chi Chou; Chung-Kuan Cheng; T. C. Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Local ratio cut and set covering partitioning for huge logic emulation systems. - Nan-Chi Chou; Lung-Tien Liu; Chung-Kuan Cheng; Wei-Jin Dai; Rodney Lindelof (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

On general zero-skew clock net construction. - Nan-Chi Chou; Chung-Kuan Cheng (IEEE Trans. Very Large Scale Integr. Syst., 1995)

An algebraic multigrid solver for analytical placement with layout based clustering. - Hongyu Chen 001; Chung-Kuan Cheng; Nan-Chi Chou; Andrew B. Kahng; John F. MacDonald; Peter Suaris; Bo Yao 004; Zhengyong Zhu (DAC, 2003)

A physical retiming algorithm for field programmable gate arrays. - Peter Suaris; Dongsheng Wang 012; Pei-Ning Guo; Nan-Chi Chou (FPGA, 2003)

A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. - Dongsheng Wang 012; Peter Suaris; Nan-Chi Chou (PATMOS, 2003)

Fast adders in modern FPGAs. - Jianhua Liu; Michael Chang; Chung-Kuan Cheng; John F. MacDonald; Nan-Chi Chou; Peter Suaris (FPGA, 2004)

Incremental physical resynthesis for timing optimization. - Peter Suaris; Lung-Tien Liu; Yuzheng Ding; Nan-Chi Chou (FPGA, 2004)

A practical cut-based physical retiming algorithm for field programmable gate arrays. - Peter Suaris; Dongsheng Wang 012; Nan-Chi Chou (ASP-DAC, 2005)

The effect of post-layout pin permutation on timing. - Yuzheng Ding; Peter Suaris; Nan-Chi Chou (FPGA, 2005)

Improving the efficiency of static timing analysis with false paths. - Shuo Zhou; Bo Yao 004; Hongyu Chen 001; Yi Zhu 002; Chung-Kuan Cheng; Michael D. Hutton; Truman Collins; Sridhar Srinivasan; Nan-Chi Chou; Peter Suaris (ICCAD, 2005)

Unified quadratic programming approach for mixed mode placement. - Bo Yao 004; Hongyu Chen 001; Chung-Kuan Cheng; Nan-Chi Chou; Lung-Tien Liu; Peter Suaris (ISPD, 2005)

Efficient Timing Analysis With Known False Paths Using Biclique Covering. - Shuo Zhou; Bo Yao 004; Hongyu Chen 001; Yi Zhu 002; Michael D. Hutton; Truman Collins; Sridhar Srinivasan; Nan-Chi Chou; Peter Suaris; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. - Renshen Wang; Nan-Chi Chou; Bill Salefski; Chung-Kuan Cheng (DAC, 2009)

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. - Renshen Wang; Yulei Zhang 002; Nan-Chi Chou; Evangeline F. Y. Young; Chung-Kuan Cheng; Ronald L. Graham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)