A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. - Hao-I Yang; Shih-Chi Yang; Mao-Chih Hsia; Yung-Wei Lin; Yi-Wei Lin; Chien-Hen Chen; Chi-Shin Chang; Geng-Cing Lin; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; et al. (SoCC, 2011)

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. - Shao-Cheng Wang; Geng-Cing Lin; Yi-Wei Lin; Ming-Chien Tsai; Yi-Wei Chiu; Shyh-Jye Jou; Ching-Te Chuang; Nan-Chun Lien; Wei-Chiang Shih; Kuen-Di Lee; Jyun-Kai Chu (APCCAS, 2012)

An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. - Geng-Cing Lin; Shao-Cheng Wang; Yi-Wei Lin; Ming-Chien Tsai; Ching-Te Chuang; Shyh-Jye Jou; Nan-Chun Lien; Wei-Chiang Shih; Kuen-Di Lee; Jyun-Kai Chu (ISCAS, 2012)

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. - Hao-I Yang; Yi-Wei Lin; Mao-Chih Hsia; Geng-Cing Lin; Chi-Shin Chang; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Nan-Chun Lien; Hung-Yu Li; Kuen-Di Lee; et al. (ISCAS, 2012)

A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. - Yung-Wei Lin; Hao-I Yang; Mao-Chih Hsia; Yi-Wei Lin; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Nan-Chun Lien; Kuen-Di Lee; Wei-Chiang Shih; Ya-Ping Wu; Wen-Ta Lee; et al. (SoCC, 2012)

An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. - Yi-Wei Lin; Ming-Chien Tsai; Hao-I Yang; Geng-Cing Lin; Shao-Cheng Wang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Nan-Chun Lien; Kuen-Di Lee; Wei-Chiang Shih (VLSI-DAT, 2012)

Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. - Ming-Chien Tsai; Yi-Wei Lin; Hao-I Yang; Ming-Hsien Tu; Wei-Chiang Shih; Nan-Chun Lien; Kuen-Di Lee; Shyh-Jye Jou; Ching-Te Chuang; Wei Hwang (VLSI-DAT, 2012)

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. - Chi-Shin Chang; Hao-I Yang; Wei-Nan Liao; Yi-Wei Lin; Nan-Chun Lien; Chien-Hen Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Ming-Hsien Tu; Huan-Shun Huang; Yong-Jyun Hu; et al. (ISCAS, 2013)

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. - Wei-Nan Liao; Nan-Chun Lien; Chi-Shin Chang; Li-Wei Chu; Hao-I Yang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Ming-Hsien Tu; Huan-Shun Huang; Jian-Hao Wang; Paul-Sen Kan; et al. (SoCC, 2013)

Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation. - Nan-Chun Lien; Ching-Te Chuang; Wen-Rong Wu (SoCC, 2013)

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. - Nan-Chun Lien; Li-Wei Chu; Chien-Hen Chen; Hao-I Yang; Ming-Hsien Tu; Paul-Sen Kan; Yong-Jyun Hu; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; et al. (IEEE J. Solid State Circuits, 2021)