Parallelized radix-2 scalable Montgomery multiplier. - Nan Jiang 009; David Money Harris (VLSI-SoC, 2007)

A MIPS R2000 implementation. - Nathaniel Ross Pinckney; Thomas Barr; Michael Dayringer; Matthew McKnett; Nan Jiang 009; Carl Nygaard; David Money Harris; Joel Stanley; Braden Phillips (DAC, 2008)

Indirect adaptive routing on large scale interconnection networks. - Nan Jiang 009; John Kim 001; William J. Dally (ISCA, 2009)

Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. - George Michelogiannakis; Nan Jiang 009; Daniel Becker 003; William J. Dally (IEEE Comput. Archit. Lett., 2011)

Network congestion avoidance through Speculative Reservation. - Nan Jiang 009; Daniel U. Becker; George Michelogiannakis; William J. Dally (HPCA, 2012)

Adaptive Backpressure: Efficient buffer management for on-chip networks. - Daniel U. Becker; Nan Jiang 009; George Michelogiannakis; William J. Dally (ICCD, 2012)

A detailed and flexible cycle-accurate Network-on-Chip simulator. - Nan Jiang 009; Daniel U. Becker; George Michelogiannakis; James D. Balfour; Brian Towles; David E. Shaw; John Kim 001; William J. Dally (ISPASS, 2013)

Channel reservation protocol for over-subscribed channels and destinations. - George Michelogiannakis; Nan Jiang 009; Daniel Becker 003; William J. Dally (SC, 2013)

Network endpoint congestion control for fine-grained communication. - Nan Jiang 009; Larry R. Dennison; William J. Dally (SC, 2015)

Exploiting idle resources in a high-radix switch for supplemental storage. - Matthias A. Blumrich; Nan Jiang 009; Larry R. Dennison (SC, 2018)

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. - Rangharajan Venkatesan; Yakun Sophia Shao; Brian Zimmer; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Hot Chips Symposium, 2019)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (MICRO, 2019)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (VLSI Circuits, 2019)

An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives. - Benjamin Klenk; Nan Jiang 009; Greg Thorson; Larry Dennison (ISCA, 2020)

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (IEEE J. Solid State Circuits, 2020)

Need for Speed: Experiences Building a Trustworthy System-Level GPU Simulator. - Oreste Villa; Daniel Lustig; Zi Yan; Evgeny Bolotin; Yaosheng Fu; Niladrish Chatterjee; Nan Jiang 009; David W. Nellans (HPCA, 2021)

Simba: scaling deep-learning inference with chiplet-based architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Commun. ACM, 2021)