A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC. - Xinkai Chen; Xiaoyu Zhang; Lingwei Zhang 001; Xiaowen Li; Nan Qi 002; Hanjun Jiang; Zhihua Wang 001 (IEEE Trans. Biomed. Circuits Syst., 2009)

A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS. - Nan Qi 002; Yang Xu 005; Baoyong Chi; Yang Xu 039; Xiaobao Yu; Xing Zhang; Zhihua Wang 001 (CICC, 2011)

A hybrid approach to I/Q imbalance self-calibration in reconfigurable low-IF receivers. - Yang Xu 005; Nan Qi 002; Zhou Chen; Baoyong Chi; Zhihua Wang 001 (ISCAS, 2012)

A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration. - Nan Qi 002; Yang Xu 005; Baoyong Chi; Yang Xu 039; Xiaobao Yu; Xing Zhang; Ni Xu; Patrick Chiang 001; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver. - Yang Xu 005; Baoyong Chi; Xiaobao Yu; Nan Qi 002; Patrick Chiang 001; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

An asymmetric dual-channel reconfigurable receiver for GNSS in 180nm CMOS. - Nan Qi 002; Baoyong Chi; Yang Xu 005; Zhou Chen; Jun Xie; Yang Xu 039; Zheng Song 002; Zhihua Wang 001 (CICC, 2013)

A 180nm fully-integrated dual-channel reconfigurable receiver for GNSS interoperations. - Nan Qi 002; Baoyong Chi; Yang Xu 039; Zhou Chen; Yang Xu 005; Jun Xie; Zheng Song 002; Zhihua Wang 001 (ESSCIRC, 2013)

A multi-mode complex bandpass filter with gm-assisted power optimization and I/Q calibration. - Nan Qi 002; Zheng Song 002; Baoyong Chi; Albert Z. Wang; Tianling Ren; Zhihua Wang 001 (ISCAS, 2013)

A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers. - Zheng Song 002; Nan Qi 002; Baoyong Chi; Zhihua Wang 001 (ASP-DAC, 2014)

9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS. - Jiao Cheng; Nan Qi 002; Patrick Yin Chiang; Arun Natarajan 001 (ISSCC, 2014)

A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS. - Jiao Cheng; Nan Qi 002; Patrick Yin Chiang; Arun Natarajan 001 (IEEE J. Solid State Circuits, 2014)

A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring system. - Shuo Li; Nan Qi 002; Vahid Behravan; Zhiliang Hong; Patrick Yin Chiang (ASICON, 2015)

22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS. - Hao Li 047; Zhe Xuan; Alex Titriku; Cheng Li; Kunzhi Yu; Binhao Wang; Ayman Shafik; Nan Qi 002; Yang Liu 178; Ran Ding; Tom Baehr Jones; Marco Fiorentino; et al. (ISSCC, 2015)

A 25Gb/s, 520mW, 6.4Vpp Silicon-Photonic Mach-Zehnder Modulator with distributed driver in CMOS. - Nan Qi 002; Xianyao Li; Hao Li 047; Xi Xiao; Lei Wang 187; Zhiyong Li 014; Zhuo Gao; Yude Yu; Miki Moyal; Patrick Chiang 001 (OFC, 2015)

A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS. - Hao Li 047; Zhe Xuan; Alex Titriku; Cheng Li; Kunzhi Yu; Binhao Wang; Ayman Shafik; Nan Qi 002; Yang Liu 178; Ran Ding; Tom Baehr Jones; Marco Fiorentino; et al. (IEEE J. Solid State Circuits, 2015)

A 32Gb/s NRZ, 25GBaud/s PAM4 reconfigurable, Si-Photonic MZM transmitter in CMOS. - Nan Qi 002; Xi Xiao; Shang Hu; Miaofeng Li; Hao Li 047; Zhiyong Li 014; Patrick Chiang 001 (OFC, 2016)

A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ΔΣ ADC With AntiPole-Splitting Opamp and Digital I/Q Calibration. - Yang Xu 005; Zehong Zhang; Baoyong Chi; Nan Qi 002; Hualin Cai; Zhihua Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector. - Jianfu Lin; Zheng Song 002; Nan Qi 002; Woogeun Rhee; Baoyong Chi (A-SSCC, 2017)

A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. - Nan Qi 002; Yuhang Kang; Qipeng Lin; Jianxu Ma; Jingbo Shi; Bozhi Yin; Chang Liu; Rui Bai 001; Shang Hu; Juncheng Wang; Jiangbing Du; Lin Ma 008; et al. (A-SSCC, 2017)

A low-power 2.4GHz ZigBee transceiver with inductor-less RF front-end for IoT applications. - Bing Xia; Nan Qi 002; Liyuan Liu; Nanjian Wu (MWSCAS, 2017)

A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS. - Juncheng Wang; Xuefeng Chen 004; Shang Hu; Yaxin Cai; Rui Bai 001; Xin Wang 130; Yuanxi Zhang; Shenglong Zhuo; Chang Liu; Bozhi Yin; Jianxu Ma; Hao Yan; et al. (A-SSCC, 2018)

A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Nan Qi 002; Peng Feng 001; Jian Liu 021; Nanjian Wu (A-SSCC, 2018)

A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter. - Cheng Li; Kunzhi Yu; Jinsoo Rhim; Kehan Zhu; Nan Qi 002; Marco Fiorentino; Thierry Pinguet; Mark Peterson; Vishal Saxena; Samuel Palermo (BCICTS, 2018)

A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation. - Chang Liu; Bozhi Yin; Tingyu Yao; Nan Qi 002; Dan Li 011; Jingbo Shi; Juncheng Wang; Hu Shang; Rui Bai 001; Patrick Yin Chiang (OFC, 2018)

Low-power 2.4 GHz ZigBee transceiver with inductor-less radio-frequency front-end for Internet of things applications. - Bing Xia; Nan Qi 002 (IET Circuits Devices Syst., 2018)

A 77-GHz Mixed-Mode FMCW Signal Generator Based on Bang-Bang Phase Detector. - Jianfu Lin; Zheng Song 002; Nan Qi 002; Woogeun Rhee; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2018)

Design of High-Speed Drivers for 56Gb/s PAM4 Optical Communications in CMOS. - Nan Qi 002; Nanjian Wu (ASICON, 2019)

A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. - Shang Hu; Tingyu Yao; Bozhi Yin; Chunyu Song; Lei Zhao; Juncheng Wang; Lei Wang 187; Rui Bai 001; Xin Wang 130; Tao Xia; Yi Peng; Binbin Yao; et al. (OFC, 2019)

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits. - Jincheng Yang; Zhao Zhang 004; Nan Qi 002; Liyuan Liu; Jian Liu 021; Nanjian Wu (Sci. China Inf. Sci., 2019)

0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Nan Qi 002; Peng Feng 001; Jian Liu 021; Nanjian Wu (IET Circuits Devices Syst., 2019)

A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS. - Juncheng Wang; Quan Pan 002; Yajie Qin; Xuefeng Chen 004; Shang Hu; Rui Bai 001; Xin Wang 130; Yaxin Cai; Tao Xia; Yuanxi Zhang; Jianxu Ma; Nan Qi 002; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Nan Qi 002; Peng Feng 001; Jian Liu 021; Nanjian Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 28GBaud High-Swing Linear Mach-Zehnder Modulators Driver for PAM-4 and Coherent Optical Communications. - Kai Hao; Jian He; Leliang Li; Shuangming Yu; Liyuan Liu; Jian Liu 021; Ningmei Yu; Nanjian Wu; Nan Qi 002 (ICTA, 2020)

A High-Speed Parallel FPGA Implementation of Harris Corner Detection. - Hongtao Zhou; Runjiang Dou; Shuangming Yu; Nan Qi 002; Jian Liu 021; Nanjian Wu; Liyuan Liu (ICTA, 2020)

A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS. - Dan Li 011; Shengwei Gao; Yongjun Shi; Xiaoyan Gui; Nan Qi 002; Zhiyong Li 014; Quan Pan 002; Patrick Chiang 001; Li Geng (ISCAS, 2020)

A 50Gb/s PAM-4 Optical Receiver with Si-Photonic PD and Linear TIA in 40nm CMOS. - Yang Liu 178; Nan Qi 002; Xiuli Xu; Weizhong Li; Lei Wang 187; Minjia Chen; Qixiang Cheng; Jingbo Shi; Liyuan Liu; Jian Liu 021; Xi Xiao; Nanjian Wu (ISCAS, 2020)

A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS. - Qiwen Liao; Nan Qi 002; Miaofeng Li; Shang Hu; Jian He; Bozhi Yin; Jingbo Shi; Jian Liu 021; Patrick Yin Chiang; Xi Xiao; Nanjian Wu (IEEE J. Solid State Circuits, 2020)

100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects. - Donglai Lu; Jian He; Weizhong Li; Sikai Chen; Jian Liu 021; Nanjian Wu; Ningmei Yu; Liyuan Liu; Yong Chen 005; Xi Xiao; Nan Qi 002 (APCCAS, 2021)

A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR. - Qiwen Liao; Miaofeng Li; Zhao Zhang 004; Jian Liu 021; Nanjian Wu; Xi Xiao; Nan Qi 002 (CICC, 2021)

A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology. - Tong Fang; Min Liu 021; Liyuan Liu; Ziteng Cai; Runjiang Dou; Peng Feng 001; Nan Qi 002; Zhao Zhang 004; Jian Liu 021; Nanjian Wu (ICTA, 2021)

A Fast-Transient Capacitor-Less Low-Dropout Regulator for Wideband Optical Transceivers. - Han Liu; Guike Li; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yingtao Li; Nan Qi 002 (ICTA, 2021)

A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects. - Mingyang You; Minjia Chen; Yihong Li; Guike Li; Jian Liu 021; Yong Chen 005; Yingtao Li; Nan Qi 002 (ICTA, 2021)

A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects. - Ming Zhong; Qingwen Wang; Yong Chen 005; Jian Liu 021; Liyuan Liu; Xinghua Wang; Xiaoming Xiong; Nan Qi 002 (ICTA, 2021)

A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. - Yihong Li; Sikai Chen; Yunqi Yang; Qianli Ma; Ming Zhong; Ziyi Lin; Leliang Li; Guike Li; Zhao Zhang 004; Liyuan Liu; Jian Liu 021; Nanjian Wu; et al. (APCCAS, 2022)

A 0.004-mm2 O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL. - Yixi Li; Xinyu Shen; Zhaoyu Zhang; Guike Li; Tao Yin; Nan Qi 002; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Zhao Zhang 004 (APCCAS, 2022)

A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop. - Zhaoyu Zhang; Xinyu Shen; Yixi Li; Guike Li; Nan Qi 002; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Zhao Zhang 004 (APCCAS, 2022)

A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers. - Sikai Chen; Jintao Xue; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Liyuan Liu; Binhao Wang; Yingtao Li; Nan Qi 002 (ICTA, 2022)

Floorplanning and Power/Ground Network Design for A Programmable Vision Chip. - Haozhe Xu; Siyuan Wei; Nan Qi 002; Peng Wu; Jian Liu 021; Nanjian Wu; Liyuan Liu; Shuangming Yu (ICTA, 2022)

A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O. - Yunqi Yang; Ming Zhong; Qianli Ma; Ziyi Lin; Leliang Li; Guike Li; Liyuan Liu; Jian Liu 021; Nanjian Wu; Haikun Jia; Xinghui Liu; Nan Qi 002 (ICTA, 2022)

A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector. - Xinyi Ge; Yong Chen 005; Lin Wang 115; Nan Qi 002; Pui-In Mak; Rui Paulo Martins (NorCAS, 2022)

A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. - Qiwen Liao; Yuguang Zhang; Siyuan Ma; Lei Wang 187; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Xi Xiao; et al. (IEEE J. Solid State Circuits, 2022)

Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects. - Jian He; Donglai Lu; Haiyun Xue; Sikai Chen; Han Liu; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Liyuan Liu; Nanjian Wu; Ningmei Yu; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. - Jian He; Yuguang Zhang; Han Liu; Qiwen Liao; Zhao Zhang 004; Miaofeng Li; Fan Jiang; Jingbo Shi; Jian Liu 021; Nanjian Wu; Yong Chen 005; Patrick Yin Chiang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. - Yixi Li; Zhao Zhang 004; Yong Chen 005; Xinyu Shen; Nan Qi 002; Jian Liu 021; Nanjian Wu; Liyuan Liu (A-SSCC, 2023)

A $ boldsymbol{4} times boldsymbol{112}- mathbf{Gb}/ mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics. - Han Liu; Nan Qi 002; Donglai Lu; Zizheng Dong; Zhihan Zhang; Jian He; Guike Li; Leliang Li; Ye Liu; Ziyue Dang; Daigao Chen; Zhao Zhang 004; et al. (A-SSCC, 2023)

A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $ boldsymbol{2.7} mathbf{pA}/ mathbf{Hz}^{ boldsymbol{0.5}}$ Input Referred Noise, and 103 $ mathbf{dB} mathbf{ Omega}$ Transimpedance Gain. - Yidan Zhang; Zhao Zhang 004; Yiqing Xu; Xinyu Shen; Nan Qi 002; Nanjian Wu; Jian Liu 021; Liyuan Liu (A-SSCC, 2023)

A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. - Xinyu Shen; Zhao Zhang 004; Guike Li; Yong Chen 005; Nan Qi 002; Jian Liu 021; Nanjian Wu; Liyuan Liu (ESSCIRC, 2023)

A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE. - Zhaoyu Zhang; Zhao Zhang 004; Yong Chen 005; Guoqing Wang; Xinyu Shen; Nan Qi 002; Guike Li; Shuangming Yu; Jian Liu 021; Nanjian Wu; Liyuan Liu (ESSCIRC, 2023)

A 400-Gb/s 64-QAM Optical Receiver with Monolithically Integrated TIA and Balanced-PD in 45-nm SOI CMOS. - Yongliang Xiong; Yihao Yang; Qianli Ma; Yangming Ren; Leliang Li; Guike Li; Jian Liu 021; Yingtao Li; Binhao Wang; Nan Qi 002; Liyuan Liu (ICTA, 2023)

An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers. - Jingbo Shi; Han Liu; Tao Yang; Ming Jin; Haowen Shu; Fenghe Yang; Lei Shi; Yuansheng Tao; Jianrui Deng; Ruixuan Chen; Changhao Han; Jian Liu 021; et al. (ISCAS, 2023)

A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. - Zhao Zhang 004; Xinyu Shen; Zhaoyu Zhang; Guike Li; Nan Qi 002; Jian Liu 021; Yong Chen 005; Nanjian Wu; Liyuan Liu (ISSCC, 2023)

A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. - Zhao Zhang 004; Zhaoyu Zhang; Yong Chen 005; Nan Qi 002; Jian Liu 021; Nanjian Wu; Liyuan Liu (VLSI Technology and Circuits, 2023)

A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. - Sikai Chen; Mingyang You; Yunqi Yang; Ye Jin; Ziyi Lin; Yihong Li; Leliang Li; Guike Li; Yujun Xie; Zhao Zhang 004; Binhao Wang; Ningfeng Tang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 200Gb/s, 3.5pJ/bit Monolithically Integrated WDM SiPhotonic Transceiver for Chiplet Optical I/O. - Qianli Ma; Ang Li; Yongliang Xiong; Yingjie Ma; Haoran Yin; Han Liu; Minye Zhu; Menghan Yang; Ye Jin; Daofa Wang; Peng Wang; Yang Qu; et al. (A-SSCC, 2024)

A 13.75-14.75-GHz 32.1-fsRMS Jitter -100.6-dBc Reference Spur -261.4-dB FoM Sub-Sampling PLL Using a KPD-Doubled Isolated Sub-Sampling Phase Detector for Reliable Spur-Jitter-Joint Optimization. - Yiqing Xu; Yixi Li; Zhao Zhang 004; Nan Qi 002; Jian Liu 021; Nanjian Wu; Liyuan Liu (A-SSCC, 2024)

A 64Gb/s Si-Photonic Micro-Ring Resonator Transceiver with Co-designed CMOS Driver and TIA for WDM Optical-IO. - Qianli Ma; Sikai Chen; Jintao Xue; Yingjie Ma; Yuean Gu; Chao Cheng; Yihan Chen; Haoran Yin; Guike Li; Zhao Zhang 004; Nanjian Wu; Ke Li; et al. (BCICTS, 2024)

A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation. - Xinyu Shen; Zhao Zhang 004; Yong Chen 005; Yixi Li; Yidan Zhang; Guike Li; Nan Qi 002; Jian Liu 021; Nanjian Wu; Liyuan Liu (CICC, 2024)

A 64-GBaud 64-QAM Optical Coherent Transmitter with Monolithically Integrated Driver and I/Q Modulator in 45-nm SOI CMOS. - Yizhou Xu; Ruogu Deng; Jingbo Wang; Han Liu; Zhihan Zhang; Yihao Yang; Guike Li; Binhao Wang; Nan Qi 002; Liyuan Liu (ICTA, 2024)

A 32Gb/s NRZ Low-Bias DFB Driver with Frequency Boosting for High Efficiency Data Transmission. - Yang Min; Yi Zhang; Tao Yang; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Nanjian Wu; Yonghui Lin; Huiyao Peng; Jingbo Shi; Nan Qi 002 (ISCAS, 2024)

A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile Edge Vision. - Xu Yang 017; Chunhe Yao; Lei Kang; Qian Luo; Nan Qi 002; Runjiang Dou; Shuangming Yu; Peng Feng 001; Zhongming Wei; Jian Liu 021; Kaiyou Wang; Nanjian Wu; et al. (IEEE J. Solid State Circuits, 2024)

A 4×112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics. - Han Liu; Zhihan Zhang; Ye Liu; Daigao Chen; Donglai Lu; Jian He; Guike Li; Min Liu 021; Ziyue Dang; Xi Xiao; Nan Qi 002 (IEEE J. Solid State Circuits, 2024)

A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2nd Harmonic Extraction Achieving 45.8fsrms Jitter and -254.3dB FoM. - Yunbo Huang; Zunsong Yang; Hongyu Ren; Rui Paulo Martins; Yan Lu 002; Nan Sun 001; Nan Qi 002; Yong Chen 005 (CICC, 2025)

19.8 A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61 dBc in-Band Fractional Spur in 40nm CMOS. - Xinyu Shen; Zhao Zhang 004; Yixi Li; Junjie Chen; Xiangjian Kong; Nan Qi 002; Jian Liu 021; Nanjian Wu; Liyuan Liu (ISSCC, 2025)

A 4λ×128Gb/s PAM-4 Si-Photonic Transmitter with Micro-Ring Modulator and Co-designed Linear Driver for Chiplet Optical I/O. - Siyuan Ma; Yingjie Ma; Chaoyang Dai; Sikai Chen; Qianli Ma; Yihan Chen; Haoran Yin; Yujun Xie; Guike Li; Jian Liu 021; Ming Li; Liyuan Liu; et al. (OFC, 2025)

A Six-Phase Harmonic-Rejection Digital Transmitter. - Jiaxiang Li; Zimu Li; Yun Yin; Changgu Yan; Nan Qi 002; Ming Liu 022; Hongtao Xu (IEEE J. Solid State Circuits, 2025)

A Monolithically Integrated DWDM Si-Photonics Transceiver for Chiplet Optical I/O. - Nan Qi 002; Qianli Ma; Ang Li; Minye Zhu; Ruoyu Wu; Yongliang Xiong; Yingjie Ma; Haoran Yin; Han Liu; Menghan Yang; Daofa Wang; Peng Wang; et al. (IEEE J. Solid State Circuits, 2025)

A 56-Gb/s, 6.3-pJ/bit PAM-4 DFB Laser Driver Incorporating Asymmetric Equalization and Integrated CDR in 28 nm CMOS. - Yang Min; Nan Qi 002; Yihan Chen; Yi Zhang; Minye Zhu; Guike Li; Yonghui Lin; Huiyao Peng; Mo Guang; Kaiwen Long; Zhao Zhang 004; Jian Liu 021; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2025)