A simple and efficient dithering method for vector quantizer based mismatch-shaped ΔΣ DACs. - Arindam Sanyal; Nan Sun 001 (ISCAS, 2012)

A single SAR ADC converting multi-channel sparse signals. - Wenjuan Guo; Youngchun Kim; Arindam Sanyal; Ahmed H. Tewfik; Nan Sun 001 (ISCAS, 2013)

A fast radix-3 SAR analog-to-digital converter. - Long Chen 004; Manzur Rahman; Sha Liu; Nan Sun 001 (MWSCAS, 2013)

A very high energy-efficiency switching technique for SAR ADCs. - Arindam Sanyal; Nan Sun 001 (MWSCAS, 2013)

Thermal Noise Analysis of a Programmable-Gain Switched-Capacitor Amplifier With Input Offset Cancellation. - Kareem Ragab; Mücahit Kozak; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping. - Arindam Sanyal; Kareem Ragab; Long Chen 004; T. R. Viswanathan 001; Shouli Yan; Nan Sun 001 (CICC, 2014)

A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique. - Long Chen 004; Arindam Sanyal; Ji Ma; Nan Sun 001 (ESSCIRC, 2014)

Capacitor mismatch calibration for SAR ADCs based on comparator metastability detection. - Long Chen 004; Ji Ma; Nan Sun 001 (ISCAS, 2014)

Algorithm and implementation of digital calibration of fast converging Radix-3 SAR ADC. - Manzur Rahman; Long Chen 004; Nan Sun 001 (ISCAS, 2014)

A low frequency-dependence, energy-efficient switching technique for bottom-plate sampled SAR ADC. - Arindam Sanyal; Nan Sun 001 (ISCAS, 2014)

An enhanced ISI shaping technique for multi-bit ΔΣ DACs. - Arindam Sanyal; Nan Sun 001 (ISCAS, 2014)

An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs. - Arindam Sanyal; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A Thermometer-Like Mismatch Shaping Technique With Minimum Element Transition Activity for Multibit ΔΣ DACs. - Arindam Sanyal; Peijun Wang; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction. - Long Chen 004; Xiyuan Tang; Arindam Sanyal; Yeonam Yoon; Jie Cong; Nan Sun 001 (CICC, 2015)

A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-based 0-1 MASH ADC with direct digital background nonlinearity calibration. - Kareem Ragab; Nan Sun 001 (CICC, 2015)

A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration. - Yeonam Yoon; Kyoungtae Lee; Sungjin Hong; Xiyuan Tang; Long Chen 004; Nan Sun 001 (CICC, 2015)

Dynamic Element Matching Techniques for Static and Dynamic Errors in Continuous-Time Multi-Bit ΔΣ Modulators. - Arindam Sanyal; Nan Sun 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization. - Kareem Ragab; Long Chen 004; Arindam Sanyal; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Novel Hybrid Radix-3/Radix-2 SAR ADC With Fast Convergence and Low Hardware Complexity. - Manzur Rahman; Arindam Sanyal; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit ΔΣ Modulators. - Arindam Sanyal; Long Chen 004; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration. - Jeonggoo Song; Kareem Ragab; Xiyuan Tang; Nan Sun 001 (A-SSCC, 2016)

A surrogate model assisted evolutionary algorithm for computationally expensive design optimization problems with discrete variables. - Bo Liu 003; Nan Sun 001; Qingfu Zhang 001; Vic Grout; Georges G. E. Gielen (CEC, 2016)

A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOS. - Shaolan Li; Nan Sun 001 (ESSCIRC, 2016)

A 1.4mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40nm CMOS. - Kareem Ragab; Nan Sun 001 (ESSCIRC, 2016)

A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS. - Arindam Sanyal; Nan Sun 001 (ESSCIRC, 2016)

A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS. - Xiyuan Tang; Long Chen 004; Jeonggoo Song; Nan Sun 001 (ESSCIRC, 2016)

Comparator common-mode variation effects analysis and its application in SAR ADCs. - Long Chen 004; Arindam Sanyal; Ji Ma; Xiyuan Tang; Nan Sun 001 (ISCAS, 2016)

A 18.5-fJ/step VCO-based 0-1 MASH ΔΣ ADC with digital background calibration. - Arindam Sanyal; Nan Sun 001 (VLSI Circuits, 2016)

A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration. - Miguel Gandara; Paridhi Gulati; Nan Sun 001 (A-SSCC, 2017)

A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator. - Xiyuan Tang; Long Chen 004; Jeonggoo Song; Nan Sun 001 (A-SSCC, 2017)

A pipelined SAR ADC reusing the comparator as residue amplifier. - Miguel Gandara; Wenjuan Guo; Xiyuan Tang; Long Chen 004; Yeonam Yoon; Nan Sun 001 (CICC, 2017)

A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS. - Jeonggoo Song; Xiyuan Tang; Nan Sun 001 (CICC, 2017)

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology. - Biying Xu; Shaolan Li; Nan Sun 001; David Z. Pan (DAC, 2017)

NFC-enabled, tattoo-like stretchable biosensor manufactured by "cut-and-paste" method. - Hyoyoung Jeong; Taewoo Ha; Irene Kuang; Linxiao Shen; Zhaohe Dai; Nan Sun 001; Nanshu Lu (EMBC, 2017)

Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits. - Biying Xu; Shaolan Li; Xiaoqing Xu; Nan Sun 001; David Z. Pan (ISPD, 2017)

Integrated CMOS spectrometer for multi-dimensional NMR spectroscopy. - Dongwan Ha; Nan Sun 001; Jeffrey Paulsen; Yi-Qiao Song; Yiqiao Tang; Sungjin Hong; Donhee Ham (MWSCAS, 2017)

A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction. - Long Chen 004; Xiyuan Tang; Arindam Sanyal; Yeonam Yoon; Jie Cong; Nan Sun 001 (IEEE J. Solid State Circuits, 2017)

A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS. - Shaolan Li; Abhishek Mukherjee; Nan Sun 001 (IEEE J. Solid State Circuits, 2017)

A 12-b ENOB 2.5-MHz BW VCO-Based 0-1 MASH ADC With Direct Digital Background Calibration. - Kareem Ragab; Nan Sun 001 (IEEE J. Solid State Circuits, 2017)

An Energy-Efficient Hybrid SAR-VCO ΔΣ Capacitance-to-Digital Converter in 40-nm CMOS. - Arindam Sanyal; Nan Sun 001 (IEEE J. Solid State Circuits, 2017)

A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration. - Jeonggoo Song; Kareem Ragab; Xiyuan Tang; Nan Sun 001 (IEEE J. Solid State Circuits, 2017)

A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS. - Long Chen 004; Kareem Ragab; Xiyuan Tang; Jeonggoo Song; Arindam Sanyal; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. - Yi Zhong; Shaolan Li; Arindam Sanyal; Xiyuan Tang; Linxiao Shen; Siliang Wu; Nan Sun 001 (A-SSCC, 2018)

Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC. - Arindam Sanyal; Shaolan Li; Nan Sun 001 (ISCAS, 2018)

A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure. - Shaolan Li; Bo Qiao 005; Miguel Gandara; Nan Sun 001 (ISSCC, 2018)

A 0.029MM2 17-FJ/Conv.-Step CT $ Delta Sigma$ ADC with 2nd-Order Noise-Shaping SAR Quantizer. - Jiaxin Liu; Shaolan Li; Wenjuan Guo; Guangjun Wen; Nan Sun 001 (VLSI Circuits, 2018)

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure. - Shaolan Li; Bo Qiao 005; Miguel Gandara; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2018)

A 1-V 0.25-µW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor. - Linxiao Shen; Nanshu Lu; Nan Sun 001 (IEEE J. Solid State Circuits, 2018)

A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration. - Dengquan Li; Jiaxin Liu; Haoyu Zhuang; Zhangming Zhu; Yintang Yang; Nan Sun 001 (CICC, 2019)

A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. - Shaolan Li; Biying Xu; David Z. Pan; Nan Sun 001 (CICC, 2019)

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure. - Shaolan Li; Wenda Zhao; Biying Xu; Xiangxing Yang; Xiyuan Tang; Linxiao Shen; Nanshu Lu; David Z. Pan; Nan Sun 001 (CICC, 2019)

A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. - Xiyuan Tang; Yi Shen 007; Linxiao Shen; Wenda Zhao; Zhangming Zhu; Visvesh Sathe 001; Nan Sun 001 (CICC, 2019)

A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction. - Yanlong Zhang; Arindam Sanyal; Xing Quan; Kailin Wen; Xiyuan Tang; Gang Jin; Li Geng; Nan Sun 001 (CICC, 2019)

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. - Biying Xu; Yibo Lin; Xiyuan Tang; Shaolan Li; Linxiao Shen; Nan Sun 001; David Z. Pan (DAC, 2019)

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. - Biying Xu; Keren Zhu 001; Mingjie Liu; Yibo Lin; Shaolan Li; Xiyuan Tang; Nan Sun 001; David Z. Pan (ICCAD, 2019)

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. - Keren Zhu 001; Mingjie Liu; Yibo Lin; Biying Xu; Shaolan Li; Xiyuan Tang; Nan Sun 001; David Z. Pan (ICCAD, 2019)

Device Layer-Aware Analytical Placement for Analog Circuits. - Biying Xu; Shaolan Li; Chak-Wa Pui; Derong Liu 002; Linxiao Shen; Yibo Lin; Nan Sun 001; David Z. Pan (ISPD, 2019)

A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor. - Linxiao Shen; Yi Shen 007; Xiyuan Tang; Chen-Kai Hsu; Wei Shi 011; Shaolan Li; Wenda Zhao; Abhishek Mukherjee; Nan Sun 001 (ISSCC, 2019)

A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. - Xiyuan Tang; Shaolan Li; Linxiao Shen; Wenda Zhao; Xiangxing Yang; Randy Williams; Jiaxin Liu; Zhichao Tan; Neal A. Hall; Nan Sun 001 (ISSCC, 2019)

A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping. - Chen-Kai Hsu; Nan Sun 001 (VLSI Circuits, 2019)

A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. - Linxiao Shen; Abhishek Mukherjee; Shaolan Li; Xiyuan Tang; Nanshu Lu; Nan Sun 001 (VLSI Circuits, 2019)

An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. - Xiyuan Tang; Begum Kasap; Linxiao Shen; Xiangxing Yang; Wei Shi 011; Nan Sun 001 (VLSI Circuits, 2019)

Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs. - Shaolan Li; Arindam Sanyal; Kyoungtae Lee; Yeonam Yoon; Xiyuan Tang; Yi Zhong; Kareem Ragab; Nan Sun 001 (IEICE Trans. Electron., 2019)

A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer. - Jiaxin Liu; Shaolan Li; Wenjuan Guo; Guangjun Wen; Nan Sun 001 (IEEE J. Solid State Circuits, 2019)

A Two-Step ADC With a Continuous-Time SAR-Based First Stage. - Linxiao Shen; Nan Sun 001; Yi Shen 007; Zhelu Li; Wei Shi 011; Xiyuan Tang; Shaolan Li; Wenda Zhao; Mantian Zhang; Zhangming Zhu (IEEE J. Solid State Circuits, 2019)

A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting. - Haoyu Zhuang; Wenjuan Guo; Jiaxin Liu; He Tang; Zhangming Zhu; Long Chen 004; Nan Sun 001 (IEEE J. Solid State Circuits, 2019)

A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration. - Dengquan Li; Zhangming Zhu; Ruixue Ding; Maliang Liu; Yintang Yang; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters. - Jiaxin Liu; Chen-Kai Hsu; Xiyuan Tang; Shaolan Li; Guangjun Wen; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration. - Jeonggoo Song; Kareem Ragab; Xiyuan Tang; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. - Mingjie Liu; Wuxi Li; Keren Zhu 001; Biying Xu; Yibo Lin; Linxiao Shen; Xiyuan Tang; Nan Sun 001; David Z. Pan (ASP-DAC, 2020)

A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC. - Xin Xin 005; Linxiao Shen; Xiyuan Tang; Yi Shen 007; Jueping Cai; Nan Sun 001 (A-SSCC, 2020)

A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping. - Chen-Kai Hsu; Xiyuan Tang; Wenda Zhao; Rui Xu 008; Abhishek Mukherjee; Timothy R. Andeen; Nan Sun 001 (CICC, 2020)

A Fully-Dynamic Time-Interleaved Noise-Shaping SAR ADC Based on CIFF Architecture. - Haoyu Zhuang; Jiaxin Liu; Nan Sun 001 (CICC, 2020)

GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. - Hanrui Wang 002; Kuan Wang; Jiacheng Yang; Linxiao Shen; Nan Sun 001; Hae-Seung Lee; Song Han 003 (DAC, 2020)

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. - Mingjie Liu; Keren Zhu 001; Xiyuan Tang; Biying Xu; Wei Shi 011; Nan Sun 001; David Z. Pan (DAC, 2020)

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. - Mingjie Liu; Keren Zhu 001; Jiaqi Gu 002; Linxiao Shen; Xiyuan Tang; Nan Sun 001; David Z. Pan (DATE, 2020)

Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. - Keren Zhu 001; Hao Chen 059; Mingjie Liu; Xiyuan Tang; Nan Sun 001; David Z. Pan (ICCAD, 2020)

Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. - Hao Chen 059; Keren Zhu 001; Mingjie Liu; Xiyuan Tang; Nan Sun 001; David Z. Pan (ICCAD, 2020)

An Energy-Efficient Flexible Capacitive Pressure Sensing System. - Yuxuan Huang; Qinghang Zhao; Xiyuan Tang; Fang Su; Nan Sun 001; Huazhong Yang; Yongpan Liu (ISCAS, 2020)

16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation. - Jiaxin Liu; Xiyuan Tang; Wenda Zhao; Linxiao Shen; Nan Sun 001 (ISSCC, 2020)

9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping. - Jiaxin Liu; Xing Wang; Zijie Gao; Mingtao Zhan; Xiyuan Tang; Nan Sun 001 (ISSCC, 2020)

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. - Xiyuan Tang; Xiangxing Yang; Wenda Zhao; Chen-Kai Hsu; Jiaxin Liu; Linxiao Shen; Abhishek Mukherjee; Wei Shi 011; David Z. Pan; Nan Sun 001 (ISSCC, 2020)

A Portable NMR System with 50-kHz IF, 10-us Dead Time, and Frequency Tracking. - Sungjin Hong; Nan Sun 001 (VLSI Circuits, 2020)

A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW. - Zhelu Li; Arnab Dutta 004; Abhishek Mukherjee; Xiyuan Tang; Linxiao Shen; Lenian He; Nan Sun 001 (VLSI Circuits, 2020)

A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation. - Xiyuan Tang; Yi Shen 007; Xin Xin 005; Shubin Liu; Jueping Cai; Zhangming Zhu; Nan Sun 001 (VLSI Circuits, 2020)

An Always-on 4× Compressive VGA CMOS Imager with 51pJ/Pixel and >32dB PSNR. - Wenda Zhao; Chanmin Park; Injun Park; Nan Sun 001; Youngcheol Chae (VLSI Circuits, 2020)

A New Method Based on Coding Sequence Density to Cluster Bacteria. - Nan Sun 001; Rui Dong; Shaojun Pei; Changchuan Yin; Stephen S.-T. Yau (J. Comput. Biol., 2020)

A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping. - Chen-Kai Hsu; Timothy R. Andeen; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

An OTA-Less Second-Order VCO-Based CT $ Delta Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback. - Shaolan Li; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration. - Dengquan Li; Zhangming Zhu; Jiaxin Liu; Haoyu Zhuang; Yintang Yang; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation. - Jiaxin Liu; Xiyuan Tang; Wenda Zhao; Linxiao Shen; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. - Yi Shen 007; Xiyuan Tang; Linxiao Shen; Wenda Zhao; Xin Xin 005; Shubin Liu; Zhangming Zhu; Visvesh Sathe 001; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

Guest Editorial 2019 Custom Integrated Circuits Conference. - Nan Sun 001; Qun Jane Gu (IEEE J. Solid State Circuits, 2020)

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. - Xiyuan Tang; Shaolan Li; Xiangxing Yang; Linxiao Shen; Wenda Zhao; Randall P. Williams; Jiaxin Liu; Zhichao Tan; Neal A. Hall; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. - Xiyuan Tang; Linxiao Shen; Begum Kasap; Xiangxing Yang; Wei Shi 011; Abhishek Mukherjee; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. - Xiyuan Tang; Xiangxing Yang; Wenda Zhao; Chen-Kai Hsu; Jiaxin Liu; Linxiao Shen; Abhishek Mukherjee; Wei Shi 011; Shaolan Li; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A Fractional-N PLL With Space-Time Averaging for Quantization Noise Reduction. - Yanlong Zhang; Arindam Sanyal; Xueyi Yu; Xing Quan; Kailin Wen; Xiyuan Tang; Gang Jin; Li Geng; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure. - Wenda Zhao; Shaolan Li; Biying Xu; Xiangxing Yang; Xiyuan Tang; Linxiao Shen; Nanshu Lu; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. - Yi Zhong; Shaolan Li; Xiyuan Tang; Linxiao Shen; Wenda Zhao; Siliang Wu; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks. - Haoyu Zhuang; Xiaodan Xi; Nan Sun 001; Michael Orshansky (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. - Hao Chen 059; Mingjie Liu; Xiyuan Tang; Keren Zhu 001; Abhishek Mukherjee; Nan Sun 001; David Z. Pan (CICC, 2021)

An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer. - Yi Zhong; Xiyuan Tang; Jiaxin Liu; Wenda Zhao; Shaolan Li; Nan Sun 001 (CICC, 2021)

DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. - Ahmet Faruk Budak; Prateek Bhansali; Bo Liu 003; Nan Sun 001; David Z. Pan; Chandramouli V. Kashyap (DAC, 2021)

Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. - Hao Chen 059; Keren Zhu 001; Mingjie Liu; Xiyuan Tang; Nan Sun 001; David Z. Pan (DAC, 2021)

A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching. - Chengyu Huang 001; Yushen Fu; Zekun Yang; Yang Liu; Nan Sun 001; Xueqing Li 002; Huazhong Yang (ESSCIRC, 2021)

OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. - Mingjie Liu; Xiyuan Tang; Keren Zhu 001; Hao Chen 059; Nan Sun 001; David Z. Pan (ICCAD, 2021)

27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering. - Jiaxin Liu; Dengquan Li; Yi Zhong; Xiyuan Tang; Nan Sun 001 (ISSCC, 2021)

A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR. - Linxiao Shen; Zijie Gao; Xiangxing Yang; Wei Shi 011; Nan Sun 001 (ISSCC, 2021)

10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. - Wei Shi 011; Jiaxin Liu; Abhishek Mukherjee; Xiangxing Yang; Xiyuan Tang; Linxiao Shen; Wenda Zhao; Nan Sun 001 (ISSCC, 2021)

A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. - Xiyuan Tang; Xiangxing Yang; Jiaxin Liu; Wei Shi 011; David Z. Pan; Nan Sun 001 (ISSCC, 2021)

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. - Jinshan Yue; Xiaoyu Feng; Yifan He 003; Yuxuan Huang; Yipeng Wang 009; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hung; et al. (ISSCC, 2021)

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. - Hao Chen 059; Mingjie Liu; Biying Xu; Keren Zhu 001; Xiyuan Tang; Shaolan Li; Yibo Lin; Nan Sun 001; David Z. Pan (IEEE Des. Test, 2021)

A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping. - Chen-Kai Hsu; Xiyuan Tang; Jiaxin Liu; Rui Xu 008; Wenda Zhao; Abhishek Mukherjee; Timothy R. Andeen; Nan Sun 001 (IEEE J. Solid State Circuits, 2021)

A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping. - Jiaxin Liu; Xing Wang; Zijie Gao; Mingtao Zhan; Xiyuan Tang; Chen-Kai Hsu; Nan Sun 001 (IEEE J. Solid State Circuits, 2021)

A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. - Abhishek Mukherjee; Miguel Gandara; Xiangxing Yang; Linxiao Shen; Xiyuan Tang; Chen-Kai Hsu; Nan Sun 001 (IEEE J. Solid State Circuits, 2021)

A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing. - Chanmin Park; Wenda Zhao; Injun Park; Nan Sun 001; Youngcheol Chae (IEEE J. Solid State Circuits, 2021)

A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC. - Haoyu Zhuang; Jiaxin Liu; He Tang; Xizhu Peng; Nan Sun 001 (IEEE J. Solid State Circuits, 2021)

Portable CMOS NMR System With 50-kHz IF, 10-μs Dead Time, and Frequency Tracking. - Sungjin Hong; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 3-Phase Resonant Switched-Capacitor Converter for Data Center 48-V Rack Power Distribution. - Chuang Wang 004; Yan Lu 002; Nan Sun 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

High-Precision ADC Testing With Relaxed Reference Voltage Stationarity. - Vivek Varier; Nan Sun 001 (IEEE Trans. Instrum. Meas., 2021)

Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. - Keren Zhu 001; Hao Chen 059; Mingjie Liu; Xiyuan Tang; Wei Shi 011; Nan Sun 001; David Z. Pan (ASP-DAC, 2022)

A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM. - Wei Shi 011; Xing Wang; Xiyuan Tang; Abhishek Mukherjee; Raviteja Theertham; Shanthi Pavan; Lu Jie 001; Nan Sun 001 (CICC, 2022)

A Fast Converging Correlation-Based Background Timing Skew Calibration Technique by Digital Windowing for Time-Interleaved ADCs. - Yunsong Tao; Kareem Ragab; Jin Shao; Pengpeng Chen; Yi Zhong; Lu Jie 001; Nan Sun 001 (ISCAS, 2022)

A Second-Order VCO-Based ΔΣ ADC with Fully Digital Feedback Summation. - Chaoyang Xing; Yi Zhong; Jin Shao; Pengpeng Chen; Lu Jie 001; Nan Sun 001 (ISCAS, 2022)

A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR. - Lu Jie 001; Mingtao Zhan; Xiyuan Tang; Nan Sun 001 (ISSCC, 2022)

A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp. - Mingtao Zhan; Lu Jie 001; Xiyuan Tang; Nan Sun 001 (ISSCC, 2022)

RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. - Wei Shi 011; Hanrui Wang 002; Jiaqi Gu 002; Mingjie Liu; David Z. Pan; Song Han 003; Nan Sun 001 (MLCAD, 2022)

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. - Ahmet Faruk Budak; Miguel Gandara; Wei Shi 011; David Z. Pan; Nan Sun 001; Bo Liu 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation. - Yi Shen 007; Xiyuan Tang; Xin Xin 005; Shubin Liu; Zhangming Zhu; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. - Xiyuan Tang; Jiaxin Liu; Yi Shen 007; Shaolan Li; Linxiao Shen; Arindam Sanyal; Kareem Ragab; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking. - Zhishuai Zhang; Zijie Gao; Siyu Huang; Nan Sun 001; Lu Jie 001 (CICC, 2023)

An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS. - Yi Zhong; Mingtao Zhan; Wei Wang; Xiyuan Tang; Lu Jie 001; Nan Sun 001 (CICC, 2023)

A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA. - Haoyu Zhuang; Nan Sun 001; Yirui Cao; Linzhi Tao; Qiang Li 021 (CICC, 2023)

A Fully-Dynamic kT/C-Noise-Canceled SAR ADC with Trimming-Free Dynamic Amplifier. - Haoyu Zhuang; Nan Sun 001; Linzhi Tao; Yizhan Li; Oiang Li (CICC, 2023)

A 3.7mW 11b 1GS/s Time-Interleaved SAR ADC with Robust One-Stage Correlation-Based Background Timing-Skew Calibration. - Mingyang Gu; Yunsong Tao; Xiyu He; Yi Zhong; Lu Jie 001; Nan Sun 001 (ESSCIRC, 2023)

A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors. - Mingyang Gu; Yi Zhong; Lu Jie 001; Nan Sun 001 (ESSCIRC, 2023)

A 0.021mm2 92dB-SNDR 88kHz-BW Incremental Zoom ADC with 2nd-order RT-DEM and Quiet Chopping. - Chaoyang Xing; Yi Zhong; Nan Sun 001; Lu Jie 001 (ESSCIRC, 2023)

LeCA: In-Sensor Learned Compressive Acquisition for Efficient Machine Vision on the Edge. - Tianrui Ma; Adith Jagadish Boloor; Xiangxing Yang; Weidong Cao 001; Patrick Williams; Nan Sun 001; Ayan Chakrabarti; Xuan Zhang 001 (ISCA, 2023)

A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor. - Mingtao Zhan; Lu Jie 001; Nan Sun 001 (ISSCC, 2023)

A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing. - Yu-Cheng Lin; Chanmin Park; Wenda Zhao; Nan Sun 001; Youngcheol Chae; Chia-Hsiang Yang (VLSI Technology and Circuits, 2023)

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. - Jinshan Yue; Mingtao Zhan; Zi Wang; Yifan He 002; Yaolei Li; Songming Yu; Wenyu Sun; Lu Jie 001; Chunmeng Dou; Xueqing Li 002; Nan Sun 001; Huazhong Yang; et al. (VLSI Technology and Circuits, 2023)

A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC. - Xin Xin 005; Linxiao Shen; Xiyuan Tang; Yi Shen 007; Jueping Cai; Xingyuan Tong; Nan Sun 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An In-Memory-Computing Charge-Domain Ternary CNN Classifier. - Xiangxing Yang; Keren Zhu 001; Xiyuan Tang; Meizhi Wang; Mingtao Zhan; Nanshu Lu; Jaydeep P. Kulkarni; David Z. Pan; Yongpan Liu; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging. - Yushen Fu; Chengyu Huang 001; Longqiang Lai; Nan Sun 001; Xueqing Li 002; Huazhong Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. - Xiyuan Tang; Xiangxing Yang; Jiaxin Liu; Zongnan Wang; Wei Shi 011; David Z. Pan; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion. - Xiangxing Yang; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor. - Mingtao Zhan; Lu Jie 001; Yi Zhong; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

A 1.2GS/s 11b Time-Interleaved SAR ADC with Low-Cost Derivative-Based Background Timing-Skew Calibration and Variable-Load Comparators. - Mingyang Gu; Yunsong Tao; Xiyu He; Yi Zhong; Lu Jie 001; Nan Sun 001 (A-SSCC, 2024)

A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS. - Chengyu Huang 001; Kezhuo Ma; Sihao Chen; Jiaxuan Fan; Nan Sun 001; Huazhong Yang; Xueqing Li 002 (CICC, 2024)

A 92.9dB-SNDR 178.2dB-FoMs SAR ADC with kT/C noise cancellation and FIA. - Zijie Gao; Yi Zhong; Lu Jie 001; Nan Sun 001 (ICTA, 2024)

A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs. - Yunsong Tao; Yi Zhong; Jin Shao; Changyou Men; Lu Jie 001; Nan Sun 001 (ISCAS, 2024)

9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs. - Xiyu He; Mingyang Gu; Hanjun Jiang; Yi Zhong; Nan Sun 001; Lu Jie 001 (ISSCC, 2024)

22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration. - Yunsong Tao; Mingyang Gu; Baoyong Chi; Yi Zhong; Lu Jie 001; Nan Sun 001 (ISSCC, 2024)

Mitigating Sampling Noise for Energy-Efficient ADCs: A Tutorial Brief. - Chang Liu; Jiaxin Liu; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. - Jinshan Yue; Yongpan Liu; Xiaoyu Feng; Yifan He 002; Jingyu Wang 004; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hong; et al. (IEEE J. Solid State Circuits, 2024)

A 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp. - Mingtao Zhan; Lu Jie 001; Xiyuan Tang; Yi Zhong; Nan Sun 001 (IEEE J. Solid State Circuits, 2024)

A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2nd Harmonic Extraction Achieving 45.8fsrms Jitter and -254.3dB FoM. - Yunbo Huang; Zunsong Yang; Hongyu Ren; Rui Paulo Martins; Yan Lu 002; Nan Sun 001; Nan Qi; Yong Chen 005 (CICC, 2025)

A Power-Efficient Jitter-Insensitive 3.2GHz 1-bit CT ΔΣ ADC with Direct Charge Dump Feedback. - Yanquan Luo; Lu Jie 001; Nan Sun 001 (CICC, 2025)

A 0.16mm2450MHz-BW 72dB-SNDR Continuous-time Pipeline ADC with APF+HPF and APF+FIR Hybrid Delay Alignment Techniques. - Heyang Zhao; Yuxuan He; Yunsong Tao; Zhishuai Zhang; Yong Chen 005; Yi Zhong; Lu Jie 001; Nan Sun 001 (CICC, 2025)

A 75-MHz-BW 3rd-order Time-Interleaved Noise-Shaping SAR ADC with Shared EF-CIFF Loop Filter and Ring Buffer. - Xiyu He; Yi Zhong; Nan Sun 001; Lu Jie 001 (ISCAS, 2025)

A Hierarchical Compilation Method for Programmable Analog-to-Digital Converter Arrays. - Zhishuai Zhang; Siyu Huang; Yi Zhong; Nan Sun 001; Lu Jie 001 (ISCAS, 2025)

Live Demonstration: A Programmable A/D Converter Array with Interactive Compiler. - Zhishuai Zhang; Chitian Yuan; Jiantao Li; Kun Lin; Yi Zhong; Nan Sun 001; Lu Jie 001 (ISCAS, 2025)

24.1 A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration. - Mingyang Gu; Yi Zhong; Lu Jie 001; Nan Sun 001 (ISSCC, 2025)

A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier. - Siyu Huang; Zhishuai Zhang; Xiyu He; Mingyang Gu; Yunsong Tao; Yi Zhong; Nan Sun 001; Lu Jie 001 (ISSCC, 2025)

An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buffer Power Gating. - Yunsong Tao; Mingtao Zhan; Mingyang Gu; Xiyu He; Yuxuan He; Zhishuai Zhang; Yi Zhong; Lu Jie 001; Nan Sun 001 (ISSCC, 2025)

3.4: A CMOS Operational Amplifier Achieving ±5.8µV 3σ Offset and ±88nV/°C 3σ Offset Drift Using an on-Chip Heater-Based Self-Trimming Technique. - Aodong Zhang; Mingtao Zhan; Mengying Chen; Yi Zhong; Lu Jie 001; Nan Sun 001; Qinwen Fan (ISSCC, 2025)

A 1-GS/s 11-b Time-Interleaved SAR ADC With Robust, Fast, and Accurate Autocorrelation-Based Background Timing-Skew Calibration. - Mingyang Gu; Yunsong Tao; Xiyu He; Yi Zhong; Lu Jie 001; Nan Sun 001 (IEEE J. Solid State Circuits, 2025)

A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving. - Sihao Chen; Chengyu Huang 001; Limeng Sun; Yang Liu; Wenjun Tang; Jiaxuan Fan; Nan Sun 001; Yong Chen 005; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

First-In-Last-Out Data Weighted Averaging Technique for Multi-Bit ΔΣ ADCs. - Xing Wang; Chaoyang Xing; Yi Zhong; Lu Jie 001; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)