A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro. - Nanbing Pan; Xiaoxin Cui; Xin Qiao; Kanglin Xiao; Qingyu Guo; Yuan Wang 001 (ISCAS, 2022)

A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Nanbing Pan; Xin'an Wang; Yuan Wang 001 (ISCAS, 2022)

A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. - Xin Qiao; Jiahao Song; Xiyuan Tang; Haoyang Luo; Nanbing Pan; Xiaoxin Cui; Runsheng Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support. - Qingyu Guo; Nanbing Pan; Xin Qiao; Xiaoxin Cui; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)