Analog Processing Based Equalizer for 40 Gbps Coherent Optical Links in 90 nm CMOS. - Pawan Kumar Moyade; Nandakumar Nambath; Allmin Ansari; Shalabh Gupta (VLSI Design, 2012)

A low power 100 Gbps DP-QPSK receiver using analog domain signal processing. - Nandakumar Nambath; Anita Gupta; Shalabh Gupta (ICNC, 2013)

Wideband Active Delay Cell Design for Analog Domain Coherent DP-QPSK Optical Receiver. - Saurabh R. Anmadwar; Nandakumar Nambath; Shalabh Gupta (VLSID, 2016)

Analog domain decision feedback equalizer for repeater-less DP-QPSK coherent optical links. - Mukul Ratwani; Rashmi Kamran; Nandakumar Nambath; Shalabh Gupta (WOCC, 2016)

First demonstration of an all analog adaptive equalizer for coherent DP-QPSK links. - Nandakumar Nambath; Mehul Anghan; Nandish Bharat Thaker; Rakesh Ashok; Rashmi Kamran; Arvind Kumar Mishra; Shalabh Gupta (OFC, 2017)

Demonstration of a polarization diversity based SH-QPSK system with CMA-DFE equalizer. - Rashmi Kamran; Nandish Bharat Thaker; Mehul Anghan; Nandakumar Nambath; Shalabh Gupta (WOCC, 2017)

A Quadrature-Phase Voltage Controlled Oscillator for Offset Phase and Frequency Compensation. - Pragya Maheshwari; Sadhu Pavan Kumar; Mukesh Deharia; Nandakumar Nambath; Shalabh Gupta (VLSID, 2018)

Adaptive Polarization Control for Coherent Optical Links with Polarization Multiplexed Carrier. - Mehul Anghan; Rashmi Kamran; Nihir Gulati; Nandakumar Nambath; Shalabh Gupta (NCC, 2019)

Hybrid Particle Swarm Optimization Algorithm for Area Minimization in 65 nm Technology. - Ria Rashid; Nandakumar Nambath (ISCAS, 2021)

Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm. - Komala Krishna; Nandakumar Nambath (CoRR, 2021)

Area Optimisation of Two Stage Miller Compensated Op-Amp in 65 nm Using Hybrid PSO. - Ria Rashid; Nandakumar Nambath (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Triple-Tail Common-Mode Insensitive High-Speed Dynamic Comparator for Analog In-Memory Computing Architectures. - Komala Krishna; Ria Rashid; Nandakumar Nambath (ISCAS, 2023)

Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS. - Komala Krishna; Nandakumar Nambath (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Performance evaluation of evolutionary algorithms for analog integrated circuit design optimisation. - Ria Rashid; Gopavaram Raghunath; Vasant Badugu; Nandakumar Nambath (Microelectron. J., 2023)

Performance Analysis of Underwater Optical Wireless Video Communication Systems. - Rajeev Kumar Kottilingal; Nandakumar Nambath (ISCAS, 2024)

High-speed cascode cross-coupled CMOS dynamic comparator with auxiliary inverter pair. - Komala Krishna; Nandakumar Nambath (Microelectron. J., 2024)

Machine learning driven global optimisation framework for analog circuit design. - Ria Rashid; Komala Krishna; Clint Pazhayidam George; Nandakumar Nambath (Microelectron. J., 2024)

Review on High-Speed Dynamic Comparators for Analog to Digital Converters. - Komala Krishna; Nandakumar Nambath (J. Circuits Syst. Comput., 2024)

Underwater Optical Wireless Data and Power Transfer System for Internet of Underwater Things. - Rajeev Kumar Kottilingal; Nandakumar Nambath (ISCAS, 2025)