On the likelihood of multiple bit upsets in logic circuits. - Nanditha P. Rao; Shahbaz Sarik; Madhav P. Desai (CoRR, 2014)

A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients. - Nanditha P. Rao; Madhav P. Desai (DSD, 2015)

Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates. - Nanditha P. Rao; Madhav P. Desai (CoRR, 2016)

Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs. - Nanditha P. Rao; Madhav P. Desai (CoRR, 2017)

Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology. - Nanditha P. Rao; Madhav P. Desai (Microelectron. J., 2018)

Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher. - Shivani Shah; Vaibhavi Mathur; Sahithi Meenakshi Vutakuru; Kavya Borra; Nanditha P. Rao (DSD, 2021)

Flush-Reload Attack and its Mitigation on an FPGA Based Compressed Cache Design. - Prashant Mata; Nanditha P. Rao (ISQED, 2021)

FPGA Accelerated Parameterized Cache Simulator. - Shivani Shah; Sahithi Meenakshi Vutakuru; Nanditha P. Rao (ISQED, 2021)

Variable Bit-Precision Vector Extension for RISC-V Based Processors. - Risikesh RK; Sharad Sinha; Nanditha P. Rao (MCSoC, 2021)

An FPGA based Tiled Systolic Array Generator to Accelerate CNNs. - Veerendra S. Devaraddi; Nanditha P. Rao (DSD, 2022)

An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs. - Alok Parmar; Kailash Prasad; Nanditha P. Rao; Joycee Mekie (ISCAS, 2022)

FastMem: A Fast Architecture-aware Memory Layout Design. - Alok Parmar; Kailash Prasad; Nanditha P. Rao; Joycee Mekie (ISQED, 2022)

Cacheaccel_Simulator. - Shivani Shah; Nanditha P. Rao (IEEE DataPort, 2022)

MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA. - Shivani Shah; Nanditha P. Rao (ACM Great Lakes Symposium on VLSI, 2023)

ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping. - Shubhayu Das; Nanditha P. Rao; Sharad Sinha (IPDPS (Workshops), 2024)