DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. - Carol Pyron; Mike Alexander; James Golab; George Joos; Bruce Long; Robert F. Molyneaux; Rajesh Raina; Nandu Tendolkar (ITC, 1999)

At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. - Nandu Tendolkar; Robert F. Molyneaux; Carol Pyron; Rajesh Raina (VTS, 2000)

Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. - Robert Bailey; A. Metayer; B. Svrcek; Nandu Tendolkar; E. Wolf; Eric Fiene; Mike Alexander; Rick Woltenberg; Rajesh Raina (ITC, 2002)

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. - Nandu Tendolkar; Rajesh Raina; Rick Woltenberg; Xijiang Lin; Bruce Swanson; Greg Aldrich (VTS, 2002)

Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture. - Nandu Tendolkar; Dawit Belete; Ashutosh Razdan; Hereman Reyes; Bill Schwarz; Marie Sullivan (ITC, 2005)

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. - Nandu Tendolkar; Dawit Belete; Bill Schwarz; Bob Podnar; Akshay Gupta; Steve Karako; Wu-Tung Cheng; Alex Babin; Kun-Han Tsai; Nagesh Tamarapalli; Greg Aldrich (ITC, 2006)