An adaptive frequency synthesizer architecture reducing reference sidebands. - Haiyong Wang; Guoliang Shou; Nanjian Wu (ISCAS, 2006)

A fast-settling PLL frequency synthesizer with direct frequency presetting. - Xiaofei Kuang; Nanjian Wu (ISSCC, 2006)

A LO-leakage auto-calibrated CMOS IEEE802.11b/g WLAN transceiver. - Haiyong Wang; Guoliang Shou; Nanjian Wu (ISCAS, 2007)

An ultra low power non-volatile memory in standard CMOS process for passive RFID tags. - Peng Feng 001; Yunlong Li; Nanjian Wu (CICC, 2009)

An accurate and fast behavioral model for PLL Frequency Synthesizer phase noise/spurs prediction. - Xiaozhou Yan; Xiaofei Kuang; Nanjian Wu (CICC, 2009)

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer. - Xiaozhou Yan; Xiaofei Kuang; Nanjian Wu (ISCAS, 2009)

A novel RFID tag chip with temperature sensor in standard CMOS process. - Qi Zhang; Peng Feng 001; Shenghua Zhou; Zhiqing Geng; Nanjian Wu (ISCAS, 2010)

Design of four-transistor Pixel for high speed CMOS image. - Yangfan Zhou; Zhongxiang Cao; Quanliang Li; Qi Qin; Nanjian Wu (ASICON, 2011)

A 2.4-GHz Energy-Efficient Transmitter for Wireless Medical Applications. - Qi Zhang; Peng Feng 001; Zhiqing Geng; Xiaozhou Yan; Nanjian Wu (IEEE Trans. Biomed. Circuits Syst., 2011)

Ultra-low-power RF transceivers for WBANs in medical applications. - Nanjian Wu; Qi Zhang (NEWCAS, 2012)

A novel architecture of local memory for programmable SIMD vision chip. - Zhe Chen; Jie Yang 033; Cong Shi 003; Nanjian Wu (ASICON, 2013)

A 2.4 GHz energy-efficient 18-Mbps FSK transmitter in 0.18 μm CMOS. - Jingjing Chen; Weiyang Liu; Peng Feng 001; Haiyong Wang; Nanjian Wu (CICC, 2013)

A Low Power 2.4 GHz RF Transceiver for ZigBee Applications. - Weiyang Liu; Jingjing Chen; Haiyong Wang; Nanjian Wu (J. Circuits Syst. Comput., 2013)

A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing. - Zhao Zhang 004; Liyuan Liu; Nanjian Wu (A-SSCC, 2014)

7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network. - Cong Shi 003; Jie Yang 033; Ye Han; Zhongxiang Cao; Qi Qin; Liyuan Liu; Nanjian Wu; Zhihua Wang 001 (ISSCC, 2014)

A 2.4 GHz low power CMOS transceiver for LR-WPAN applications. - Weiyang Liu; Jingjing Chen; Xiaodong Liu; Haiyong Wang; Nanjian Wu (Sci. China Inf. Sci., 2014)

A massively parallel keypoint detection and description (MP-KDD) algorithm for high-speed vision chip. - Cong Shi 003; Jie Yang 033; Liyuan Liu; Nanjian Wu; ZhiHua Wang 001 (Sci. China Inf. Sci., 2014)

A high speed multi-level-parallel array processor for vision chips. - Cong Shi 003; Jie Yang 033; Nanjian Wu; ZhiHua Wang 001 (Sci. China Inf. Sci., 2014)

A high speed 1000 fps CMOS image sensor with low noise global shutter pixels. - Yangfan Zhou; Zhongxiang Cao; Qi Qin; Quanliang Li; Cong Shi 003; Nanjian Wu (Sci. China Inf. Sci., 2014)

A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network. - Cong Shi 003; Jie Yang 033; Ye Han; Zhongxiang Cao; Qi Qin; Liyuan Liu; Nanjian Wu; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2014)

A novel vision chip architecture for image recognition based on convolutional neural network. - Honglong Li; Zhongxing Zhang; Jie Yang 033; Liyuan Liu; Nanjian Wu (ASICON, 2015)

An efficient layered ABV methodology for vision system on chip based on heterogeneous parallel processors. - Victor Nshunguyimfura; Jie Yang 033; Liyuan Liu; Nanjian Wu (ASICON, 2015)

A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS. - Jincheng Yang; Zhao Zhang 004; Peng Feng 001; Liyuan Liu; Nanjian Wu (ASICON, 2015)

High-speed object detection based on a hierarchical parallel vision chip. - Zhongxing Zhang; Jie Yang 033; Honglong Li; Liyuan Liu; Jian Liu 021; Nanjian Wu (ASICON, 2015)

A fully-integrated 860-GHz CMOS terahertz sensor. - Zhao-yang Liu; Liyuan Liu; Jie Yang 033; Nanjian Wu (A-SSCC, 2015)

A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor. - Yangfan Zhou; Zhongxiang Cao; Ye Han; Quanliang Li; Cong Shi 003; Runjiang Dou; Qi Qin; Jian Liu 021; Nanjian Wu (Sci. China Inf. Sci., 2015)

A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulator. - Beichen Zhang; Runjiang Dou; Liyuan Liu; Nanjian Wu (A-SSCC, 2016)

A 256×256 time-of-flight image sensor based on center-tap demodulation pixel structure. - Zhe Chen; Shan Di; Zhongxiang Cao; Qi Qin; Fei Ji; Liyuan Liu; Nanjian Wu (Sci. China Inf. Sci., 2016)

Detection of 3.0 THz wave with a detector in 65 nm standard CMOS process. - Tong Fang; Zhao-yang Liu; Liyuan Liu; Yuan-Yuan Li; Jun-qi Liu; Jian Liu 021; Nanjian Wu (A-SSCC, 2017)

A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Peng Feng 001; Jian Liu 021; Nanjian Wu (A-SSCC, 2017)

A low-power 2.4GHz ZigBee transceiver with inductor-less RF front-end for IoT applications. - Bing Xia; Nan Qi; Liyuan Liu; Nanjian Wu (MWSCAS, 2017)

Terahertz detector for imaging in 180-nm standard CMOS process. - Zhao-yang Liu; Liyuan Liu; Zhao Zhang 004; Jian Liu 021; Nanjian Wu (Sci. China Inf. Sci., 2017)

High-speed visual target tracking with mixed rotation invariant description and skipping searching. - Yongxing Yang; Jie Yang 033; Zhongxing Zhang; Liyuan Liu; Nanjian Wu (Sci. China Inf. Sci., 2017)

A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Peng Feng 001; Jian Liu 021; Nanjian Wu (IEICE Electron. Express, 2017)

High-Speed Target Tracking System Based on a Hierarchical Parallel Vision Processor and Gray-Level LBP Algorithm. - Yongxing Yang; Jie Yang 033; Liyuan Liu; Nanjian Wu (IEEE Trans. Syst. Man Cybern. Syst., 2017)

A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique. - Zhao Zhang 004; Liyuan Liu; Peng Feng 001; Nanjian Wu (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 25 fps 32 × 24 Digital CMOS Terahertz Image Sensor. - Tong Fang; Runjiang Dou; Liyuan Liu; Jian Liu 021; Nanjian Wu (A-SSCC, 2018)

A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Nan Qi; Peng Feng 001; Jian Liu 021; Nanjian Wu (A-SSCC, 2018)

Neuromorphic vision chips. - Nanjian Wu (Sci. China Inf. Sci., 2018)

A Heterogeneous Parallel Processor for High-Speed Vision Chip. - Jie Yang 033; Yongxing Yang; Zhe Chen; Liyuan Liu; Jian Liu 021; Nanjian Wu (IEEE Trans. Circuits Syst. Video Technol., 2018)

A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Peng Feng 001; Jian Liu 021; Nanjian Wu (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 8-b 1GS/s 2b/cycle SAR ADC in 28-nm CMOS. - Song Ma; Liyuan Liu; Jian Liu 021; Nanjian Wu (APCCAS, 2019)

20, 000-fps Visual Motion Magnification on Pixel-parallel Vision Chip. - Junxian He; Xichuan Zhou; Yingcheng Lin; Chonglei Sun; Cong Shi 003; Nanjian Wu; Gang Luo 003 (ASICON, 2019)

High-speed Classification of AER Data Based on a Low-cost Hardware System. - Jinguo Huang; Yingcheng Lin; Wei He; Xichuan Zhou; Cong Shi 003; Nanjian Wu; Gang Luo 003 (ASICON, 2019)

Design of High-Speed Drivers for 56Gb/s PAM4 Optical Communications in CMOS. - Nan Qi; Nanjian Wu (ASICON, 2019)

Efficient Reservoir Encoding Method for Near-Sensor Classification with Rate-Coding Based Spiking Convolutional Neural Networks. - Xu Yang 017; Shuangming Yu; Liyuan Liu; Jian Liu 021; Nanjian Wu (ISNN (2), 2019)

High-speed target tracking system based on multi-interconnection heterogeneous processor and multi-descriptor algorithm. - Jiaqing Wang; Yongxing Yang; Liyuan Liu; Nanjian Wu (Sci. China Inf. Sci., 2019)

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits. - Jincheng Yang; Zhao Zhang 004; Nan Qi; Liyuan Liu; Jian Liu 021; Nanjian Wu (Sci. China Inf. Sci., 2019)

Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. - Qian Di; Zhongxing Zhang; Honglong Li; Zhao Zhang 004; Peng Feng 001; Nanjian Wu (IEICE Electron. Express, 2019)

0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Nan Qi; Peng Feng 001; Jian Liu 021; Nanjian Wu (IET Circuits Devices Syst., 2019)

An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Nan Qi; Peng Feng 001; Jian Liu 021; Nanjian Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Method of Estimating FD Capacitance with Large Size Photodiode in High Speed Imaging (Invited Paper). - Chao Gu; Zhenhua Guo; Shuangming Yu; Liyuan Liu; Jian Liu 021; Peng Feng 001; Nanjian Wu (ICTA, 2020)

A Compact On-chip Analog Memory Cell for Storing TOF Image Signal in CMOS Process. - Zhenhua Guo; Chao Gu; Shuangming Yu; Liyuan Liu; Jian Liu 021; Peng Feng 001; Nanjian Wu (ICTA, 2020)

A 28GBaud High-Swing Linear Mach-Zehnder Modulators Driver for PAM-4 and Coherent Optical Communications. - Kai Hao; Jian He; Leliang Li; Shuangming Yu; Liyuan Liu; Jian Liu 021; Ningmei Yu; Nanjian Wu; Nan Qi (ICTA, 2020)

A High-speed Low-cost CNN Inference Accelerator for Depthwise Separable Convolution. - Yingcheng Lin; Rui Li; Wei He; Xichuan Zhou; Junxian He; Ping Li 042; Ying Jiang; Liyuan Liu; Nanjian Wu; Cong Shi 003 (ICTA, 2020)

A High-Speed Parallel FPGA Implementation of Harris Corner Detection. - Hongtao Zhou; Runjiang Dou; Shuangming Yu; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (ICTA, 2020)

A 50Gb/s PAM-4 Optical Receiver with Si-Photonic PD and Linear TIA in 40nm CMOS. - Yang Liu; Nan Qi; Xiuli Xu; Weizhong Li; Lei Wang 187; Minjia Chen; Qixiang Cheng; Jingbo Shi; Liyuan Liu; Jian Liu 021; Xi Xiao; Nanjian Wu (ISCAS, 2020)

A verification method for array-based vision chip using a fixed-point neural network simulation tool. - Mingxin Zhao; Xuemin Zheng; Ke Ning; Chunhe Yao; Qian Luo; Shuangming Yu; Liyuan Liu; Nanjian Wu (LASCAS, 2020)

Deterministic conversion rule for CNNs to efficient spiking convolutional neural networks. - Xu Yang 017; Zhongxing Zhang; Wenping Zhu; Shuangming Yu; Liyuan Liu; Nanjian Wu (Sci. China Inf. Sci., 2020)

TBC-Net: A real-time detector for infrared small target detection using semantic constraint. - Mingxin Zhao; Li Cheng 005; Xu Yang 017; Peng Feng 001; Liyuan Liu; Nanjian Wu (CoRR, 2020)

A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS. - Qiwen Liao; Nan Qi; Miaofeng Li; Shang Hu; Jian He; Bozhi Yin; Jingbo Shi; Jian Liu 021; Patrick Yin Chiang; Xi Xiao; Nanjian Wu (IEEE J. Solid State Circuits, 2020)

A Discrete-Time Audio ΔΣ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques. - Song Ma; Liyuan Liu; Tong Fang; Jian Liu 021; Nanjian Wu (IEEE J. Solid State Circuits, 2020)

A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification. - Wei He; Jinguo Huang; Tengxiao Wang; Yingcheng Lin; Junxian He; Xichuan Zhou; Ping Li 042; Ying Wang 001; Nanjian Wu; Cong Shi 003 (Sensors, 2020)

Quantizing Oriented Object Detection Network via Outlier-Aware Quantization and IoU Approximation. - Mingxin Zhao; Ke Ning; Shuangming Yu; Liyuan Liu; Nanjian Wu (IEEE Signal Process. Lett., 2020)

100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects. - Donglai Lu; Jian He; Weizhong Li; Sikai Chen; Jian Liu 021; Nanjian Wu; Ningmei Yu; Liyuan Liu; Yong Chen 005; Xi Xiao; Nan Qi (APCCAS, 2021)

Pixel Design of Ultra-high Speed CMOS Image Sensor. - Peng Feng 001; Liyuan Liu; Nanjian Wu (ASICON, 2021)

A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR. - Qiwen Liao; Miaofeng Li; Zhao Zhang 004; Jian Liu 021; Nanjian Wu; Xi Xiao; Nan Qi (CICC, 2021)

A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology. - Tong Fang; Min Liu 021; Liyuan Liu; Ziteng Cai; Runjiang Dou; Peng Feng 001; Nan Qi; Zhao Zhang 004; Jian Liu 021; Nanjian Wu (ICTA, 2021)

A Pixel-Parallel Array Processor without Computational Logic for Computational Image Sensors. - Yingcheng Lin; Rui Li; Wei He; Xichuan Zhou; Junxian He; Ping Li 042; Liyuan Liu; Nanjian Wu; Cong Shi 003 (ICTA, 2021)

A Fast-Transient Capacitor-Less Low-Dropout Regulator for Wideband Optical Transceivers. - Han Liu; Guike Li; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yingtao Li; Nan Qi (ICTA, 2021)

TripleBrain: An Edge Neuromorphic Architecture for High-accuracy Single-layer Spiking Neural Network with On-chip Self-organizing and Reinforcement Learning. - Haibing Wang; Zhen He; Jinsong Rao; Tengxiao Wang; Junxian He; Min Tian; Xichuan Zhou; Liyuan Liu; Nanjian Wu; Cong Shi 003 (ICTA, 2021)

CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features. - Tengxiao Wang; Cong Shi 003; Xichuan Zhou; Yingcheng Lin; Junxian He; Ping Gan; Ping Li 042; Ying Wang 001; Liyuan Liu; Nanjian Wu; Gang Luo 003 (Neurocomputing, 2021)

A Compact High-Quality Image Demosaicking Neural Network for Edge-Computing Devices. - Shuyu Wang; Mingxin Zhao; Runjiang Dou; Shuangming Yu; Liyuan Liu; Nanjian Wu (Sensors, 2021)

A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps. - Ling Zhang; Jing Yang 067; Cong Shi 003; Yingcheng Lin; Wei He; Xichuan Zhou; Xu Yang 004; Liyuan Liu; Nanjian Wu (Sensors, 2021)

A Low-Cost High-Speed Object Tracking VLSI System Based on Unified Textural and Dynamic Compressive Features. - Wei He; Jie Zhang; Yingcheng Lin; Xichuan Zhou; Ping Li 042; Liyuan Liu; Nanjian Wu; Cong Shi 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

DeepTempo: A Hardware-Friendly Direct Feedback Alignment Multi-Layer Tempotron Learning Rule for Deep Spiking Neural Networks. - Cong Shi 003; Tengxiao Wang; Junxian He; Jianghao Zhang; Liyuan Liu; Nanjian Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. - Yihong Li; Sikai Chen; Yunqi Yang; Qianli Ma; Ming Zhong; Ziyi Lin; Leliang Li; Guike Li; Zhao Zhang 004; Liyuan Liu; Jian Liu 021; Nanjian Wu; et al. (APCCAS, 2022)

A 0.004-mm2 O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL. - Yixi Li; Xinyu Shen; Zhaoyu Zhang; Guike Li; Tao Yin; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Zhao Zhang 004 (APCCAS, 2022)

A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop. - Zhaoyu Zhang; Xinyu Shen; Yixi Li; Guike Li; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Zhao Zhang 004 (APCCAS, 2022)

MorphBungee: An Edge Neuromorphic Chip for High-Accuracy On-Chip Learning of Multiple-Layer Spiking Neural Networks. - Tengxiao Wang; Haibing Wang; Junxian He; Zhengqing Zhong; Fang Tang; Xichuan Zhou; Shuangming Yu; Liyuan Liu; Nanjian Wu; Min Tian; Cong Shi 003 (BioCAS, 2022)

Floorplanning and Power/Ground Network Design for A Programmable Vision Chip. - Haozhe Xu; Siyuan Wei; Nan Qi; Peng Wu; Jian Liu 021; Nanjian Wu; Liyuan Liu; Shuangming Yu (ICTA, 2022)

A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O. - Yunqi Yang; Ming Zhong; Qianli Ma; Ziyi Lin; Leliang Li; Guike Li; Liyuan Liu; Jian Liu 021; Nanjian Wu; Haikun Jia; Xinghui Liu; Nan Qi (ICTA, 2022)

A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. - Qiwen Liao; Yuguang Zhang; Siyuan Ma; Lei Wang 187; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Xi Xiao; et al. (IEEE J. Solid State Circuits, 2022)

SiamMixer: A Lightweight and Hardware-Friendly Visual Object-Tracking Network. - Li Cheng 005; Xuemin Zheng; Mingxin Zhao; Runjiang Dou; Shuangming Yu; Nanjian Wu; Liyuan Liu (Sensors, 2022)

TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity. - Haibing Wang; Zhen He; Tengxiao Wang; Junxian He; Xichuan Zhou; Ying Wang 001; Liyuan Liu; Nanjian Wu; Min Tian; Cong Shi 003 (IEEE Trans. Biomed. Circuits Syst., 2022)

Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects. - Jian He; Donglai Lu; Haiyun Xue; Sikai Chen; Han Liu; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Liyuan Liu; Nanjian Wu; Ningmei Yu; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. - Jian He; Yuguang Zhang; Han Liu; Qiwen Liao; Zhao Zhang 004; Miaofeng Li; Fan Jiang; Jingbo Shi; Jian Liu 021; Nanjian Wu; Yong Chen 005; Patrick Yin Chiang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning. - Zhen He; Cong Shi 003; Tengxiao Wang; Ying Wang 001; Min Tian; Xichuan Zhou; Ping Li 042; Liyuan Liu; Nanjian Wu; Gang Luo 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Programmable and Flexible Vision Processor. - Qian Luo; Chunhe Yao; Ke Ning; Xuemin Zheng; Mingxin Zhao; Li Cheng 005; Shuangming Yu; Jian Liu 021; Nanjian Wu; Liyuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A High-Speed NMS Coprocessor for Lightweight Ship Detection Algorithm. - Ke Ning; Mingxin Zhao; Chunhe Yao; Xuemin Zheng; Mengmeng Xu; Nanjian Wu; Liyuan Liu; Shuangming Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

ViP: A Hierarchical Parallel Vision Processor for Hybrid Vision Chip. - Xuemin Zheng; Li Cheng 005; Mingxin Zhao; Qian Luo; Honglong Li; Runjiang Dou; Shuangming Yu; Nanjian Wu; Liyuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Provisional Labels-Reduced, Real-Time Connected Component Labeling Algorithm for Edge Hardware. - Hongtao Zhou; Runjiang Dou; Li Cheng 005; Jian Liu 021; Nanjian Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Exploring Structural Sparsity in CNN via Selective Penalty. - Mingxin Zhao; Junbo Peng; Shuangming Yu; Liyuan Liu; Nanjian Wu (IEEE Trans. Circuits Syst. Video Technol., 2022)

Live Demonstration: Face Recognition at The Edge Using Fast On-Chip Deep Learning Neuromorphic Chip. - Zhengqing Zhong; Tengxiao Wang; Haibing Wang; Zhihua Zhou; Junxian He; Fang Tang; Xichuan Zhou; Shuangming Yu; Liyuan Liu; Nanjian Wu; Min Tian; Cong Shi 003 (AICAS, 2023)

A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. - Yixi Li; Zhao Zhang 004; Yong Chen 005; Xinyu Shen; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (A-SSCC, 2023)

A $ boldsymbol{4} times boldsymbol{112}- mathbf{Gb}/ mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics. - Han Liu; Nan Qi; Donglai Lu; Zizheng Dong; Zhihan Zhang; Jian He; Guike Li; Leliang Li; Ye Liu; Ziyue Dang; Daigao Chen; Zhao Zhang 004; et al. (A-SSCC, 2023)

MorphBungee: A 65nm 7.2mm2 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network Learning. - Tengxiao Wang; Min Tian; Zhengqing Zhong; Haibing Wang; Junxian He; Fang Tang; Xichuan Zhou; Shuangming Yu; Nanjian Wu; Liyuan Liu; Cong Shi 003 (A-SSCC, 2023)

A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $ boldsymbol{2.7} mathbf{pA}/ mathbf{Hz}^{ boldsymbol{0.5}}$ Input Referred Noise, and 103 $ mathbf{dB} mathbf{ Omega}$ Transimpedance Gain. - Yidan Zhang; Zhao Zhang 004; Yiqing Xu; Xinyu Shen; Nan Qi; Nanjian Wu; Jian Liu 021; Liyuan Liu (A-SSCC, 2023)

A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. - Xinyu Shen; Zhao Zhang 004; Guike Li; Yong Chen 005; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (ESSCIRC, 2023)

A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE. - Zhaoyu Zhang; Zhao Zhang 004; Yong Chen 005; Guoqing Wang; Xinyu Shen; Nan Qi; Guike Li; Shuangming Yu; Jian Liu 021; Nanjian Wu; Liyuan Liu (ESSCIRC, 2023)

A Lightweight Integer-STBP On-Chip Learning Method of Spiking Neural Networks For Edge Processors. - Fuming Lei; Xu Yang 017; Jian Liu 021; Nanjian Wu; Cong Shi 003; Runjiang Dou; Liyuan Liu (ICTA, 2023)

A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process. - Guoqing Wang; Zhao Zhang 004; Xinyu Shen; Zhaoyu Zhang; Jian Liu 021; Nanjian Wu; Liyuan Liu (ICTA, 2023)

A 128×128 15µm-Pitch DROIC with Pixel-Level 14-Bit ADC. - Huanhui Zhang; Xu Yang 017; Zhe Wang; Shuangming Yu; Peng Feng 001; Jian Liu 021; Nanjian Wu; Runjiang Dou; Liyuan Liu (ICTA, 2023)

An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers. - Jingbo Shi; Han Liu; Tao Yang; Ming Jin; Haowen Shu; Fenghe Yang; Lei Shi; Yuansheng Tao; Jianrui Deng; Ruixuan Chen; Changhao Han; Jian Liu 021; et al. (ISCAS, 2023)

A 16.4kPixel 3.08-to-3.86THz Digital Real-Time CMOS Image Sensor with 73dB Dynamic Range. - Min Liu 021; Ziteng Cai; Shaohua Zhou; Man-Kay Law; Jian Liu 021; Jianguo Ma; Nanjian Wu; Liyuan Liu (ISSCC, 2023)

A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. - Zhao Zhang 004; Xinyu Shen; Zhaoyu Zhang; Guike Li; Nan Qi; Jian Liu 021; Yong Chen 005; Nanjian Wu; Liyuan Liu (ISSCC, 2023)

A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. - Zhao Zhang 004; Zhaoyu Zhang; Yong Chen 005; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (VLSI Technology and Circuits, 2023)

Hierarchical Parallel Vision Processor for High-Speed Ship Detection. - Mengmeng Xu; Zhongxing Zhang; Honglong Li; Qian Luo; Runjiang Dou; Liyuan Liu; Jian Liu 021; Nanjian Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Low-cost real-time VLSI system for high-accuracy optical flow estimation using biological motion features and random forests. - Cong Shi 003; Junxian He; Shrinivas J. Pundlik; Xichuan Zhou; Nanjian Wu; Gang Luo 003 (Sci. China Inf. Sci., 2023)

An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips. - Leyi Chen; Cong Shi 003; Junxian He; Jianyi Yu; Haibing Wang; Jing Lu; Liyuan Liu; Nanjian Wu; Min Tian (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. - Sikai Chen; Mingyang You; Yunqi Yang; Ye Jin; Ziyi Lin; Yihong Li; Leliang Li; Guike Li; Yujun Xie; Zhao Zhang 004; Binhao Wang; Ningfeng Tang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods. - Lei Kang; Xu Yang 017; Chi Zhang; Shuangming Yu; Runjiang Dou; Wenchang Li; Cong Shi 003; Jian Liu 021; Nanjian Wu; Liyuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 75.6Gb/S 22-Bit Floating-Point Reconfigurable DSP Accelerator Embedding 2048×256-Point Complex FFT and 26K-Point 1-D Signal Processing. - Xuanzhe Xu; Xianjun Liu; Siyuan Wei; Shuangming Yu; Runjiang Dou; Xu Yang 017; Zhe Wang; Jian Liu 021; Nanjian Wu; Liyuan Liu (A-SSCC, 2024)

A 13.75-14.75-GHz 32.1-fsRMS Jitter -100.6-dBc Reference Spur -261.4-dB FoM Sub-Sampling PLL Using a KPD-Doubled Isolated Sub-Sampling Phase Detector for Reliable Spur-Jitter-Joint Optimization. - Yiqing Xu; Yixi Li; Zhao Zhang 004; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (A-SSCC, 2024)

A 64Gb/s Si-Photonic Micro-Ring Resonator Transceiver with Co-designed CMOS Driver and TIA for WDM Optical-IO. - Qianli Ma; Sikai Chen; Jintao Xue; Yingjie Ma; Yuean Gu; Chao Cheng; Yihan Chen; Haoran Yin; Guike Li; Zhao Zhang 004; Nanjian Wu; Ke Li; et al. (BCICTS, 2024)

A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation. - Xinyu Shen; Zhao Zhang 004; Yong Chen 005; Yixi Li; Yidan Zhang; Guike Li; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (CICC, 2024)

Edge-type High-speed Intelligent Infrared Pre-processor. - Yuxiao Wen; Runjiang Dou; Yongchao Deng; Chi Zhang; Huanhui Zhang; Shuangming Yu; Jian Liu 021; Nanjian Wu; Liyuan Liu (ICTA, 2024)

A 3μm Pixel Device for Peak Power Mitigation of Global-Shutter Indirect Time of Flight Image Sensor. - Ruotong Yin; Yinlei Liang; Weizhe Zhang; Peng Feng 001; Zhe Wang; Runjiang Dou; Jian Liu 021; Nanjian Wu; Liyuan Liu (ICTA, 2024)

Invited Paper: Area Efficient Low Power Data Transmission Circuit with Analog Differential Data Selector for CMOS Image Sensor. - Fangqiang Zhan; Weizhe Zhang; Peng Feng 001; Runjiang Dou; Jian Liu 021; Nanjian Wu; Liyuan Liu (ICTA, 2024)

A 32Gb/s NRZ Low-Bias DFB Driver with Frequency Boosting for High Efficiency Data Transmission. - Yang Min; Yi Zhang; Tao Yang; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Nanjian Wu; Yonghui Lin; Huiyao Peng; Jingbo Shi; Nan Qi (ISCAS, 2024)

A visual cortex-inspired edge neuromorphic hardware architecture with on-chip multi-layer STDP learning. - Junxian He; Min Tian; Ying Jiang; Haibing Wang; Tengxiao Wang; Xichuan Zhou; Liyuan Liu; Nanjian Wu; Ying Wang 001; Cong Shi 003 (Comput. Electr. Eng., 2024)

DT-SCNN: dual-threshold spiking convolutional neural network with fewer operations and memory access for edge applications. - Fuming Lei; Xu Yang 017; Jian Liu 021; Runjiang Dou; Nanjian Wu (Frontiers Comput. Neurosci., 2024)

A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips. - Siyuan Wei; Ke Ning; Lei Kang; Xuemin Zheng; Mingxin Zhao; Mengmeng Xu; Shuyu Wang; Xuanzhe Xu; Runjiang Dou; Shuangming Yu; Xu Yang 017; Jian Liu 021; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile Edge Vision. - Xu Yang 017; Chunhe Yao; Lei Kang; Qian Luo; Nan Qi; Runjiang Dou; Shuangming Yu; Peng Feng 001; Zhongming Wei; Jian Liu 021; Kaiyou Wang; Nanjian Wu; et al. (IEEE J. Solid State Circuits, 2024)

A 64 × 128 3D-Stacked SPAD Image Sensor for Low-Light Imaging. - Zhe Wang; Xu Yang 017; Na Tian; Min Liu 021; Ziteng Cai; Peng Feng 001; Runjiang Dou; Shuangming Yu; Nanjian Wu; Jian Liu 021; Liyuan Liu (Sensors, 2024)

A 3 THz CMOS Image Sensor. - Min Liu 021; Ziteng Cai; Zhe Wang; Shaohua Zhou; Man-Kay Law; Jian Liu 021; Jianguo Ma; Nanjian Wu; Liyuan Liu (IEEE J. Solid State Circuits, 2024)

Ghost Reservoir: A Memory-Efficient Low-Power and Real-Time Neuromorphic Processor of Liquid State Machine With On-Chip Learning. - Cong Shi 003; Xiang Fu; Haibing Wang; Yingcheng Lin; Ying Jiang; Liyuan Liu; Nanjian Wu; Min Tian (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

19.8 A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61 dBc in-Band Fractional Spur in 40nm CMOS. - Xinyu Shen; Zhao Zhang 004; Yixi Li; Junjie Chen; Xiangjian Kong; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (ISSCC, 2025)

A 56-Gb/s 0.11-pJ/bit/dB energy-efficient PAM-4 transmitter using push-pull current-mode driver and DDJ-suppressed multiplexer. - Zhaoyu Zhang; Yadong Xiao; Jian Liu 021; Nanjian Wu; Zhao Zhang 004; Liyuan Liu (IEICE Electron. Express, 2025)