Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE". - Yoshimitsu Sakagawa; Yusio Akazawa; Naoaki Narumi; Akira Yoshii; Tsuneta Sudo (ITC, 1988)

Key Technologies for 500 MHz VLSI Test System "ULTIMATE". - Teruo Tamama; Naoaki Narumi; Tai-ichi Otsuji; Masao Suzuki; Tsuneta Sudo (ITC, 1988)

A 10-ps resolution, process-insensitive timing generator IC. - Tai-ichi Otsuji; Naoaki Narumi (IEEE J. Solid State Circuits, 1989)

A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array. - Tai-ichi Otsuji; Naoaki Narumi (IEEE J. Solid State Circuits, 1991)