SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. - Kazuaki J. Murakami; Naohiko Irie; Morihiro Kuga; Shinji Tomita (ISCA, 1989)

Elastic shared resource scheduling SOC interconnect architecture for real-time system. - Makoto Saen; Hiroshi Ueda; Masaru Hase; Eiji Yamamoto; Yoshihiro Mori; Hiroshi Hatae; Yuki Kondo; Seiji Miura; Itaru Nonomura; Naohiko Irie; Hiromi Watanabe (CICC, 2005)

Hierarchical power distribution and power management scheme for a single chip mobile processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (DAC, 2006)

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (ISSCC, 2006)

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. - Makoto Saen; Kenichi Osada; Satoshi Misaka; Tetsuya Yamada; Yoshitaka Tsujimoto; Yuki Kondo; Tatsuya Kamei; Yutaka Yoshida; Ei Nagahama; Yusuke Nitta; Takayasu Ito; Tadashi Kameyama; et al. (ISSCC, 2007)

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. - Yutaka Yoshida; Tatsuya Kamei; Kiyoshi Hayase; Shinichi Shibahara; Osamu Nishii; Toshihiro Hattori; Atsushi Hasegawa; Masashi Takada; Naohiko Irie; Kunio Uchiyama; Toshihiko Odaka; Kiwamu Takada; et al. (ISSCC, 2007)

A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core. - Tetsuya Yamada; Naohiko Irie; Takanobu Tsunoda; Takahiro Irita; Kenji Kitagawa; Ryohei Yoshida; Keisuke Toyama 003; Motoaki Satoyama (IEICE Trans. Electron., 2007)

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (IEEE J. Solid State Circuits, 2007)

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. - Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Makoto Saen; Shigenobu Komatsu; Kenichi Osada; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (ISSCC, 2009)

Multi-Core/Multi-IP Technology for Embedded Applications. - Naohiko Irie; Toshihiro Hattori (IEICE Trans. Electron., 2009)

Domain Partitioning Technology for Embedded Multicore Processors. - Tohru Nojiri; Yuki Kondo; Naohiko Irie; Masayuki Ito; Hajime Sasaki; Hideo Maejima (IEEE Micro, 2009)

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. - Makoto Saen; Kenichi Osada; Yasuyuki Okuma; Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. - Kiichi Niitsu; Yoshinori Kohama; Yasufumi Sugimori; Kazutaka Kasuga; Kenichi Osada; Naohiko Irie; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. - Kiichi Niitsu; Yasufumi Sugimori; Yoshinori Kohama; Kenichi Osada; Naohiko Irie; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2011)