An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation. - Kiichi Niitsu; Masato Sakurai; Naohiro Harigai; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (A-SSCC, 2011)

Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. - Masato Sakurai; Kiichi Niitsu; Naohiro Harigai; Daiki Hirabayashi; Daiki Oki; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (ISOCC, 2011)

A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. - Kiichi Niitsu; Masato Sakurai; Naohiro Harigai; Daiki Hirabayashi; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (ASP-DAC, 2012)

A clock jitter reduction circuit using gated phase blending between self-delayed clock edges. - Kiichi Niitsu; Naohiro Harigai; Daiki Hirabayashi; Daiki Oki; Masato Sakurai; Osamu Kobayashi; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (VLSIC, 2012)

CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation. - Kiichi Niitsu; Masato Sakurai; Naohiro Harigai; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (IEEE J. Solid State Circuits, 2012)

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. - Kiichi Niitsu; Naohiro Harigai; Daiki Hirabayashi; Daiki Oki; Masato Sakurai; Osamu Kobayashi; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (ASP-DAC, 2013)

Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption. - Kiichi Niitsu; Naohiro Harigai; Haruo Kobayashi 001 (IEICE Electron. Express, 2013)

A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines. - Kiichi Niitsu; Naohiro Harigai; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (IEICE Trans. Electron., 2013)

A low-offset cascaded time amplifier with reconfigurable inter-stage connection. - Kiichi Niitsu; Naohiro Harigai; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (IEICE Electron. Express, 2014)

A CMOS PWM Transceiver Using Self-Referenced Edge Detection. - Kiichi Niitsu; Yusuke Osawa; Naohiro Harigai; Daiki Hirabayashi; Osamu Kobayashi; Takahiro J. Yamaguchi; Haruo Kobayashi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)