SimCell: A Processor Simulator for Multi-Core Architecture Research. - Shimpei Sato; Naoki Fujieda; Akira Moriya; Kenji Kise (Inf. Media Technol., 2009)

A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors. - Naoki Fujieda; Kenji Kise (ICNC, 2011)

Rethinking processor instruction fetch: Inefficiencies-cracking mechanism. - Mochamad Asri; Naoki Fujieda; Kenji Kise (ISOCC, 2011)

ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. - Shinya Takamaeda-Yamazaki; Shintaro Sano; Yoshito Sakaguchi; Naoki Fujieda; Kenji Kise (ARC, 2012)

An XOR-Based Approach to Merging Entries for Instruction Register Files. - Naoki Fujieda; Shuichi Ichikawa (CANDAR, 2013)

A Complement to Enhanced Instruction Register File against Embedded Software Falsification. - Naoki Fujieda; Kiyohiro Sato; Shuichi Ichikawa (PPREW@ACSAC, 2015)

Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM. - Naoki Fujieda; Ryo Yamauchi; Shuichi Ichikawa (CANDAR, 2016)

Design and implementation of instruction indirection for embedded software obfuscation. - Naoki Fujieda; Tasuku Tanaka; Shuichi Ichikawa (Microprocess. Microsystems, 2016)

An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis. - Yoshiki Ishigaki; Naoki Fujieda; Yuumi Matsuoka; Kazuki Uyama; Shuichi Ichikawa (CANDAR, 2017)

Evaluation of the hardwired sequence control system generated by high-level synthesis. - Naoki Fujieda; Shuichi Ichikawa; Yoshiki Ishigaki; Tasuku Tanaka (ISIE, 2017)

A Virtual Cache for Overlapped Memory Accesses of Path ORAM. - Naoki Fujieda; Ryo Yamauchi; Hiroki Fujita; Shuichi Ichikawa (Int. J. Netw. Comput., 2017)

An Analysis on Randomness of Path ORAM for Light-Weight Implementation. - Hiroki Fujita; Naoki Fujieda; Shuichi Ichikawa (CANDAR Workshops, 2018)

A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity. - Naoki Fujieda; Yusuke Ayuzawa; Masato Hongo; Shuichi Ichikawa (TENCON, 2018)

A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs. - Naoki Fujieda; Shuichi Ichikawa (IEICE Electron. Express, 2018)

Evaluation of Register Number Abstraction for Enhanced Instruction Register Files. - Naoki Fujieda; Kiyohiro Sato; Ryodai Iwamoto; Shuichi Ichikawa (IEICE Trans. Inf. Syst., 2018)

A light-weight implementation of latch-based true random number generator. - Naoki Fujieda; Hitomi Kishibe; Shuichi Ichikawa (IWCMC, 2019)

On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs. - Naoki Fujieda (FPL, 2020)

Enhanced use of mixed-mode clock manager for coherent sampling-based true random number generator. - Naoki Fujieda; Sogo Takashima (CANDAR (Workshops), 2020)

An Analysis of DCM-Based True Random Number Generator. - Naoki Fujieda; Masaaki Takeda; Shuichi Ichikawa (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Python-based evaluation framework for stochastic computing circuits on FPGA SoC. - Naoki Fujieda (CANDAR (Workshops), 2021)

A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC). - Shunsuke Matsuoka; Shuichi Ichikawa; Naoki Fujieda (Int. J. Circuit Theory Appl., 2021)

An MMCM-based high-speed true random number generator for Xilinx FPGA. - Naoki Fujieda; Sogo Takashima (Int. J. Netw. Comput., 2021)

An HLS implementation of on-the-fly randomness test for TRNGs. - Ryusei Oya; Naoki Fujieda; Shuichi Ichikawa (CANDAR, 2022)

A Novel Remote FPGA Lab Platform Using MCU-based Controller Board. - Naoki Fujieda; Atsuki Okuchi (TALE, 2023)

Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator. - Naoki Fujieda; Shuichi Ichikawa; Ryusei Oya; Hitomi Kishibe (IEICE Trans. Inf. Syst., 2023)

A case for edge video processing with FPGA SoC: reversi board detection using Hough transform. - Naoki Fujieda; Naoya Ito (CANDARW, 2024)