A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. - Akira Tanabe; Toshio Takeshima; Hiroki Koike; Yoshiharu Aimoto; Masahide Takada; Toshiyuki Ishijima; Naoki Kasai; Hiromitsu Hada; Kentaro Shibahara; Takemitsu Kunio; Takaho Tanigawa; Takanori Saeki; et al. (IEEE J. Solid State Circuits, 1992)

A 30-ns 256-Mb DRAM with a multidivided array structure. - Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; Tatsuya Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; et al. (IEEE J. Solid State Circuits, 1993)

FeRAM device and circuit technologies fully compatible with advanced CMOS. - Hideo Toyoshima; Sota Kobayashi; Junichi Yamada; Tohru Miwa; Hiroki Koike; Hidenori Takeuchi; Hidemitsu Mori; Naoki Kasai; Yukihiko Maejima; Nobuhira Tanabe; Toru Tatsumi; Hiromitsu Hada (CICC, 2001)

Special Section on Microelectronic Test Structures. - Naoki Kasai (IEICE Trans. Electron., 2005)

Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs. - Takeo Matsuki; Kazuyoshi Torii; Takeshi Maeda; Yasushi Akasaka; Kiyoshi Hayashi; Naoki Kasai; Tsunetoshi Arikado (IEICE Trans. Electron., 2005)

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode. - Takeshi Honda; Noboru Sakimura; Tadahiko Sugibayashi; Naoki Kasai; Hiromitsu Hada; Shuichi Tahara (IEICE Trans. Electron., 2007)

MRAM Applications Using Unlimited Write Endurance. - Tadahiko Sugibayashi; Takeshi Honda; Noboru Sakimura; Shuichi Tahara; Naoki Kasai (IEICE Trans. Electron., 2007)

A 16-Mb Toggle MRAM With Burst Modes. - Tadahiko Sugibayashi; Noboru Sakimura; Takeshi Honda; Kiyokazu Nagahara; Kiyotaka Tsuji; Hideaki Numata; Sadahiko Miura; Ken-ichi Shimura; Yuko Kato; Shinsaku Saito; Yoshiyuki Fukumoto; Hiroaki Honjo; et al. (IEEE J. Solid State Circuits, 2007)

A 90nm 12ns 32Mb 2T1MTJ MRAM. - Ryusuke Nebashi; Noboru Sakimura; Hiroaki Honjo; Shinsaku Saito; Yuichi Ito; Sadahiko Miura; Yuko Kato; Kaoru Mori; Yasuaki Ozaki; Yosuke Kobayashi; Norikazu Ohshima; Keizo Kinoshita; et al. (ISSCC, 2009)

Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros. - Ryusuke Nebashi; Noboru Sakimura; Tadahiko Sugibayashi; Naoki Kasai (IEICE Trans. Electron., 2009)

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs. - Noboru Sakimura; Tadahiko Sugibayashi; Ryusuke Nebashi; Naoki Kasai (IEEE J. Solid State Circuits, 2009)

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. - Ryusuke Nebashi; Noboru Sakimura; Hiroaki Honjo; Ayuka Morioka; Yukihide Tsuji; Kunihiko Ishihara; Keiichi Tokutome; Sadahiko Miura; Shunsuke Fukami; Keizo Kinoshita; Takahiro Hanyu; Tetsuo Endoh; et al. (ISCAS, 2014)

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. - Noboru Sakimura; Yukihide Tsuji; Ryusuke Nebashi; Hiroaki Honjo; Ayuka Morioka; Kunihiko Ishihara; Keizo Kinoshita; Shunsuke Fukami; Sadahiko Miura; Naoki Kasai; Tetsuo Endoh; Hideo Ohno; et al. (ISSCC, 2014)