Error Spectrum Shaping in 2-D Digital Filters. - Takao Hinamoto; Shuji Karino; Naoki Kuroda (ISCAS, 1995)

An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D2/RAM). - Yasuhiro Agata; Kenji Motomochi; Yoshifumi Fukushima; Masanori Shirahama; Marefusa Kurumada; Naoki Kuroda; Hiroyuki Sadakata; Kohtaro Hayashi; Toshio Yamada; Kazunari Takahashi; Tsutomu Fujita (IEEE J. Solid State Circuits, 2000)

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. - Masahisa Iida; Naoki Kuroda; Hidefumi Otsuka; Masanobu Hirose; Yuji Yamasaki; Kiyoto Ohta; Kazuhiko Shimakawa; Takashi Nakabayashi; Hiroyuki Yamauchi; Tomohiko Sano; Takayuki Gyohten; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2005)

A 400-MHz random-cycle dual-port interleaved DRAM (D2RAM) with standard CMOS Process. - Masanori Shirahama; Yasuhiro Agata; Toshiaki Kawasaki; Ryuji Nishihara; Wataru Abe; Naoki Kuroda; Hiroyuki Sadakata; Toshitaka Uchikoba; Kazunari Takahashi; Kyoko Egashira; Shinji Honda; Miho Miura; et al. (IEEE J. Solid State Circuits, 2005)