Aware-Mail: An Event-Driven Mail System for Wearable Computing Environments. - Naoki Miura; Masakazu Miyamae; Tsutomu Terada; Masahiko Tsukamoto; Shojiro Nishio (ICDCS Workshops, 2004)

A state-space model of the hemodynamic approach: nonlinear filtering of BOLD signals. - Jorge J. Riera; Jobu Watanabe; Kazuki Iwata; Naoki Miura; Eduardo Aubert; Tohru Ozaki; Ryuta Kawashima (NeuroImage, 2004)

The human parietal cortex is involved in spatial processing of tongue movement - an fMRI study. - Jobu Watanabe; Motoaki Sugiura; Naoki Miura; Yoshihiko Watanabe; Yasuhiro Maeda; Yoshihiko Matsue; Ryuta Kawashima (NeuroImage, 2004)

Cortical activation during reading of ancient versus modern Japanese texts: fMRI study. - Naoki Miura; Jobu Watanabe; Kazuki Iwata; Yuko Sassa; Jorge J. Riera; Hideo Tsuchiya; Shigeru Sato; Kaoru Horie; Makoto Takahashi; Masaharu Kitamura; Ryuta Kawashima (NeuroImage, 2005)

Multiple brain networks for visual self-recognition with different sensitivity for motion and body part. - Motoaki Sugiura; Yuko Sassa; Hyeonjeong Jeong; Naoki Miura; Yuko Akitsuki; Kaoru Horie; Shigeru Sato; Ryuta Kawashima (NeuroImage, 2006)

An advantage of bipedal humanoid robot on the empathy generation: A neuroimaging study. - Naoki Miura; Motoaki Sugiura; Makoto Takahashi; Tomohisa Moridaira; Atsushi Miyamoto; Yoshihiro Kuroki; Ryuta Kawashima (IROS, 2008)

Analyzing Control-Display Movement Compatibility: A Neuroimaging Study. - S. M. Hadi Hosseini; Maryam Rostami; Makoto Takahashi; Naoki Miura; Motoaki Sugiura; Ryuta Kawashima (HCI (17), 2009)

Second-language Instinct and Instruction Effects: Nature and Nurture in Second-language Acquisition. - Noriaki Yusa; Masatoshi Koizumi; Jungho Kim; Naoki Kimura; Shinya Uchida; Satoru Yokoyama; Naoki Miura; Ryuta Kawashima; Hiroko Hagiwara (J. Cogn. Neurosci., 2011)

Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs. - Naoki Miura; Akihiko Miyazaki; Junichi Kato; Nobuyuki Tanaka; Masami Urano; Mamoru Nakanishi; Tsugumichi Shibata (ISCAS, 2012)

Effectiveness of SIEPON Package B Compliant ONU Sleep Technique and Impact on Latency and Transmission Efficiency from a Theoretical Point of View. - Susumu Nishihara; Naoki Miura; Nobuyuki Tanaka; Ken-Ichi Suzuki; Naoto Yoshimoto (JOCN, 2014)

A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table. - Yoshifumi Kawamura; Kousuke Imamura; Naoki Miura; Masami Urano; Satoshi Shigematsu; Yoshio Matsuda (ISPACS, 2015)

Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip. - Naoki Miura; Akihiko Miyazaki; Junichi Kato; Nobuyuki Tanaka; Satoshi Shigematsu; Masami Urano; Mamoru Nakanishi; Tsugumichi Shibata (IEICE Trans. Electron., 2015)

A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function. - Kousuke Imamura; Ryota Honda; Yoshifumi Kawamura; Naoki Miura; Masami Urano; Satoshi Shigematsu; Tetsuya Matsumura; Yoshio Matsuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. - Akitaka Hiratsuka; Akira Tsuchiya; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (A-SSCC, 2018)

A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation. - Il-Min Yi; Naoki Miura; Hiroyuki Fukuyama; Hideyuki Nosaka (A-SSCC, 2018)

A Summer-Embedded Sense Amplifier for High-Speed Decision Feedback Equalizer. - Il-Min Yi; Naoki Miura; Hiroyuki Fukuyama; Hideyuki Nosaka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. - Akira Tsuchiya; Akitaka Hiratsuka; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (SoCC, 2019)

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. - Akira Tsuchiya; Akitaka Hiratsuka; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (IEICE Trans. Electron., 2020)

A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation. - Il-Min Yi; Naoki Miura; Hiroyuki Fukuyama; Hideyuki Nosaka (IEEE J. Solid State Circuits, 2021)

A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS. - Il-Min Yi; Naoki Miura; Hideyuki Nosaka (IEEE J. Solid State Circuits, 2021)

Japanese-English Sentence Translation Exercises Dataset for Automatic Grading. - Naoki Miura; Hiroaki Funayama; Seiya Kikuchi; Yuichiroh Matsubayashi; Yuya Iwase; Kentaro Inui (EACL (Student Research Workshop), 2024)

17.4 Environmentally-Friendly Disposable Circuit and Battery System for Reducing Impact of E-Wastes. - Naoki Miura; Hiroaki Taguchi; Kazuyoshi Watanabe; Masaya Nohara; Tatsuyuki Makita; Masahiro Tanabe; Takahiro Wakimoto; Shohei Kumagai; Hideyuki Nosaka; Atsushi Aratake; Toshihiro Okamoto; Shun Watanabe; et al. (ISSCC, 2024)