A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI. - Fuyuki Okamoto; Yasuhiko Hagihara; Chie Ohkubo; Naoki Nishi; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1991)

A Single-Chip Multiprocessor for Smart Terminals. - Masato Edahiro; Satoshi Matsushita; Masakazu Yamashina; Naoki Nishi (IEEE Micro, 2000)

Scalable bus interface for HSDPA co-processor extension. - Toshiki Takeuchi; Hiroyuki Igura; Takeshi Hashimoto; Soichi Tsumura; Naoki Nishi (CICC, 2005)

An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques. - Masahiro Nomura; Taku Ohsawa; Koichi Takeda 001; Yoetsu Nakazawa; Yoshinori Hirota; Yasuhiko Hagihara; Naoki Nishi (IEICE Trans. Electron., 2006)

RF and signal processing technologies for 4G mobile networks. - Shingo Yamanouchi; Kazuaki Kunihiro; Shinichi Hori; Masao Ikekawa; Naoki Nishi (VLSI-DAT, 2013)