A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. - Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (VLSI-SoC, 2018)

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. - Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (VLSI-SoC (Selected Papers), 2018)

A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS. - Naoki Ojima; Zule Xu; Tetsuya Iizuka (NEWCAS, 2019)

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC. - Zule Xu; Naoki Ojima; Shuowei Li; Tetsuya Iizuka (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os. - Kosuke Yanagidaira; Mario Sako; Yasuhiro Hirashima; Junya Matsuno; Yumi Higashi; Yutaka Shimizu; Akihiro Imamoto; Kazuaki Kawaguchi; Koji Tabata; Takeshi Nakano; Yusuke Ochi; Hiroaki Hoshino; et al. (ISSCC, 2025)