Development of a CMOS Data Recovery PLL for DVD-ROMx14. - Shiro Dosho; Naoshi Yanagisawa; Seiji Watanabe; Takahiro Bokui; Kazuhiko Nishikawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A background optimization method for PLL by measuring phase jitter performance. - Shiro Dosho; Naoshi Yanagisawa; Akira Matsuzawa (IEEE J. Solid State Circuits, 2005)

An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter. - Shiro Dosho; Naoshi Yanagisawa; Kazuaki Sogawa; Yuji Yamada; Takashi Morie (IEICE Trans. Electron., 2007)